From: Andre Przywara <andre.przywara@arm.com>
To: Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Ard Biesheuvel <ardb@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Marc Zyngier <maz@kernel.org>
Cc: Theodore Ts'o <tytso@mit.edu>,
Sudeep Holla <sudeep.holla@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Mark Brown <broonie@kernel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Linus Walleij <linus.walleij@linaro.org>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org,
Andre Przywara <andre.przywara@arm.com>
Subject: [PATCH v3 4/5] arm64: Add support for SMCCC TRNG entropy source
Date: Fri, 13 Nov 2020 18:24:34 +0000 [thread overview]
Message-ID: <20201113182435.64015-5-andre.przywara@arm.com> (raw)
In-Reply-To: <20201113182435.64015-1-andre.przywara@arm.com>
The ARM architected TRNG firmware interface, described in ARM spec
DEN0098, defines an ARM SMCCC based interface to a true random number
generator, provided by firmware.
This can be discovered via the SMCCC >=v1.1 interface, and provides
up to 192 bits of entropy per call.
Hook this SMC call into arm64's arch_get_random_*() implementation,
coming to the rescue when the CPU does not implement the ARM v8.5 RNG
system registers.
For the detection, we piggy back on the PSCI/SMCCC discovery (which gives
us the conduit to use (hvc/smc)), then try to call the
ARM_SMCCC_TRNG_VERSION function, which returns -1 if this interface is
not implemented.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/include/asm/archrandom.h | 69 ++++++++++++++++++++++++-----
1 file changed, 58 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrandom.h
index abe07c21da8e..fe34bfd30caa 100644
--- a/arch/arm64/include/asm/archrandom.h
+++ b/arch/arm64/include/asm/archrandom.h
@@ -4,13 +4,24 @@
#ifdef CONFIG_ARCH_RANDOM
+#include <linux/arm-smccc.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <asm/cpufeature.h>
+#define ARM_SMCCC_TRNG_MIN_VERSION 0x10000UL
+
+extern bool smccc_trng_available;
+
static inline bool __init smccc_probe_trng(void)
{
- return false;
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, &res);
+ if ((s32)res.a0 < 0)
+ return false;
+
+ return res.a0 >= ARM_SMCCC_TRNG_MIN_VERSION;
}
static inline bool __arm64_rndr(unsigned long *v)
@@ -43,26 +54,52 @@ static inline bool __must_check arch_get_random_int(unsigned int *v)
static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
{
+ struct arm_smccc_res res;
+
/*
* Only support the generic interface after we have detected
* the system wide capability, avoiding complexity with the
* cpufeature code and with potential scheduling between CPUs
* with and without the feature.
*/
- if (!cpus_have_const_cap(ARM64_HAS_RNG))
- return false;
+ if (cpus_have_const_cap(ARM64_HAS_RNG))
+ return __arm64_rndr(v);
- return __arm64_rndr(v);
-}
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, &res);
+ if ((int)res.a0 < 0)
+ return false;
+ *v = res.a3;
+ return true;
+ }
+
+ return false;
+}
static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
{
+ struct arm_smccc_res res;
unsigned long val;
- bool ok = arch_get_random_seed_long(&val);
- *v = val;
- return ok;
+ if (cpus_have_const_cap(ARM64_HAS_RNG)) {
+ if (arch_get_random_seed_long(&val)) {
+ *v = val;
+ return true;
+ }
+ return false;
+ }
+
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 32, &res);
+ if ((int)res.a0 < 0)
+ return false;
+
+ *v = res.a3 & GENMASK(31, 0);
+ return true;
+ }
+
+ return false;
}
static inline bool __init __early_cpu_has_rndr(void)
@@ -77,10 +114,20 @@ arch_get_random_seed_long_early(unsigned long *v)
{
WARN_ON(system_state != SYSTEM_BOOTING);
- if (!__early_cpu_has_rndr())
- return false;
+ if (__early_cpu_has_rndr())
+ return __arm64_rndr(v);
+
+ if (smccc_trng_available) {
+ struct arm_smccc_res res;
- return __arm64_rndr(v);
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, &res);
+ if ((int)res.a0 >= 0) {
+ *v = res.a3;
+ return true;
+ }
+ }
+
+ return false;
}
#define arch_get_random_seed_long_early arch_get_random_seed_long_early
--
2.17.1
next prev parent reply other threads:[~2020-11-13 18:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-13 18:24 [PATCH v3 0/5] ARM: arm64: Add SMCCC TRNG entropy service Andre Przywara
2020-11-13 18:24 ` [PATCH v3 1/5] firmware: smccc: Add SMCCC TRNG function call IDs Andre Przywara
2020-11-17 21:07 ` Linus Walleij
2020-11-13 18:24 ` [PATCH v3 2/5] firmware: smccc: Introduce SMCCC TRNG framework Andre Przywara
2020-11-17 21:08 ` Linus Walleij
2020-11-13 18:24 ` [PATCH v3 3/5] ARM: implement support for SMCCC TRNG entropy source Andre Przywara
2020-11-17 21:10 ` Linus Walleij
2020-11-13 18:24 ` Andre Przywara [this message]
2020-11-19 13:41 ` [PATCH v3 4/5] arm64: Add " Ard Biesheuvel
2020-11-20 10:52 ` André Przywara
2020-11-20 11:36 ` Ard Biesheuvel
2020-11-13 18:24 ` [PATCH v3 5/5] KVM: arm64: implement the TRNG hypervisor call Andre Przywara
2020-11-13 23:05 ` [PATCH v3 0/5] ARM: arm64: Add SMCCC TRNG entropy service Ard Biesheuvel
2020-11-13 23:54 ` André Przywara
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