From: Eric Auger <eric.auger@redhat.com>
To: eric.auger.pro@gmail.com, eric.auger@redhat.com,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu,
will@kernel.org, joro@8bytes.org, maz@kernel.org,
robin.murphy@arm.com
Cc: jean-philippe@linaro.org, zhangfei.gao@linaro.org,
zhangfei.gao@gmail.com, vivek.gautam@arm.com,
shameerali.kolothum.thodi@huawei.com, alex.williamson@redhat.com,
jacob.jun.pan@linux.intel.com, yi.l.liu@intel.com,
tn@semihalf.com, nicoleotsuka@gmail.com
Subject: [PATCH v12 07/15] iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs
Date: Mon, 16 Nov 2020 11:43:08 +0100 [thread overview]
Message-ID: <20201116104316.31816-8-eric.auger@redhat.com> (raw)
In-Reply-To: <20201116104316.31816-1-eric.auger@redhat.com>
With nested stage support, soon we will need to invalidate
S1 contexts and ranges tagged with an unmanaged asid, this
latter being managed by the guest. So let's introduce 2 helpers
that allow to invalidate with externally managed ASIDs
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 +++++++++++++++++----
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 08ab0dd81049..73f7a56101dd 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1679,9 +1679,9 @@ static int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain,
}
/* IO_PGTABLE API */
-static void arm_smmu_tlb_inv_context(void *cookie)
+static void __arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain,
+ int ext_asid)
{
- struct arm_smmu_domain *smmu_domain = cookie;
struct arm_smmu_device *smmu = smmu_domain->smmu;
struct arm_smmu_cmdq_ent cmd;
@@ -1692,7 +1692,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
* insertion to guarantee those are observed before the TLBI. Do be
* careful, 007.
*/
- if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
+ if (ext_asid >= 0) { /* guest stage 1 invalidation */
+ cmd.opcode = CMDQ_OP_TLBI_NH_ASID;
+ cmd.tlbi.asid = ext_asid;
+ cmd.tlbi.vmid = smmu_domain->s2_cfg->vmid;
+ } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg->cd.asid);
} else {
cmd.opcode = CMDQ_OP_TLBI_S12_VMALL;
@@ -1703,9 +1707,17 @@ static void arm_smmu_tlb_inv_context(void *cookie)
arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0);
}
-static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
+static void arm_smmu_tlb_inv_context(void *cookie)
+{
+ struct arm_smmu_domain *smmu_domain = cookie;
+
+ __arm_smmu_tlb_inv_context(smmu_domain, -1);
+}
+
+static void __arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
size_t granule, bool leaf,
- struct arm_smmu_domain *smmu_domain)
+ struct arm_smmu_domain *smmu_domain,
+ int ext_asid)
{
struct arm_smmu_device *smmu = smmu_domain->smmu;
unsigned long start = iova, end = iova + size, num_pages = 0, tg = 0;
@@ -1720,7 +1732,11 @@ static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
if (!size)
return;
- if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
+ if (ext_asid >= 0) { /* guest stage 1 invalidation */
+ cmd.opcode = CMDQ_OP_TLBI_NH_VA;
+ cmd.tlbi.asid = ext_asid;
+ cmd.tlbi.vmid = smmu_domain->s2_cfg->vmid;
+ } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
cmd.opcode = CMDQ_OP_TLBI_NH_VA;
cmd.tlbi.asid = smmu_domain->s1_cfg->cd.asid;
} else {
@@ -1780,6 +1796,13 @@ static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
arm_smmu_atc_inv_domain(smmu_domain, 0, start, size);
}
+static void arm_smmu_tlb_inv_range(unsigned long iova, size_t size,
+ size_t granule, bool leaf,
+ struct arm_smmu_domain *smmu_domain)
+{
+ __arm_smmu_tlb_inv_range(iova, size, granule, leaf, smmu_domain, -1);
+}
+
static void arm_smmu_tlb_inv_page_nosync(struct iommu_iotlb_gather *gather,
unsigned long iova, size_t granule,
void *cookie)
--
2.21.3
next prev parent reply other threads:[~2020-11-16 12:11 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-16 10:43 [PATCH v12 00/15] SMMUv3 Nested Stage Setup (IOMMU part) Eric Auger
2020-11-16 10:43 ` [PATCH v12 01/15] iommu: Introduce attach/detach_pasid_table API Eric Auger
2020-11-16 15:14 ` kernel test robot
2020-11-16 10:43 ` [PATCH v12 02/15] iommu: Introduce bind/unbind_guest_msi Eric Auger
2020-11-16 10:43 ` [PATCH v12 03/15] iommu/arm-smmu-v3: Maintain a SID->device structure Eric Auger
2020-11-16 10:43 ` [PATCH v12 04/15] iommu/smmuv3: Dynamically allocate s1_cfg and s2_cfg Eric Auger
2020-11-17 11:39 ` Shameerali Kolothum Thodi
2020-11-17 12:36 ` Auger Eric
2020-11-16 10:43 ` [PATCH v12 05/15] iommu/smmuv3: Get prepared for nested stage support Eric Auger
2020-11-16 10:43 ` [PATCH v12 06/15] iommu/smmuv3: Implement attach/detach_pasid_table Eric Auger
2020-11-16 10:43 ` Eric Auger [this message]
2020-11-16 10:43 ` [PATCH v12 08/15] iommu/smmuv3: Implement cache_invalidate Eric Auger
2020-11-16 10:43 ` [PATCH v12 09/15] dma-iommu: Implement NESTED_MSI cookie Eric Auger
2020-11-16 10:43 ` [PATCH v12 10/15] iommu/smmuv3: Nested mode single MSI doorbell per domain enforcement Eric Auger
2020-11-16 10:43 ` [PATCH v12 11/15] iommu/smmuv3: Enforce incompatibility between nested mode and HW MSI regions Eric Auger
2020-11-16 10:43 ` [PATCH v12 12/15] iommu/smmuv3: Implement bind/unbind_guest_msi Eric Auger
2020-11-16 10:43 ` [PATCH v12 13/15] iommu/smmuv3: Report non recoverable faults Eric Auger
2020-11-16 10:43 ` [PATCH v12 14/15] iommu/smmuv3: Accept configs with more than one context descriptor Eric Auger
2020-11-16 10:43 ` [PATCH v12 15/15] iommu/smmuv3: Add PASID cache invalidation per PASID Eric Auger
2020-11-16 16:24 ` kernel test robot
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