From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org,
linux-kernel@vger.kernel.org, anshuman.khandual@arm.com,
jonathan.zhouwen@huawei.com, coresight@lists.linaro.org
Subject: Re: [PATCH v4 11/25] coresight: etm4x: Define DEVARCH register fields
Date: Mon, 30 Nov 2020 14:19:08 -0700 [thread overview]
Message-ID: <20201130211908.GG1092947@xps15> (raw)
In-Reply-To: <20201119164547.2982871-12-suzuki.poulose@arm.com>
On Thu, Nov 19, 2020 at 04:45:33PM +0000, Suzuki K Poulose wrote:
> Define the fields of the DEVARCH register for identifying
> a component as an ETMv4.x unit. Going forward, we use the
> DEVARCH register for the component identification, rather
> than the TRCIDR3.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> .../coresight/coresight-etm4x-core.c | 4 +-
> drivers/hwtracing/coresight/coresight-etm4x.h | 42 +++++++++++++++++++
> 2 files changed, 44 insertions(+), 2 deletions(-)
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index c2499b62e64e..6f776f075602 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1622,8 +1622,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
> static struct amba_cs_uci_id uci_id_etm4[] = {
> {
> /* ETMv4 UCI data */
> - .devarch = 0x47704a13,
> - .devarch_mask = 0xfff0ffff,
> + .devarch = ETM_DEVARCH_ETMv4x_ARCH,
> + .devarch_mask = ETM_DEVARCH_ID_MASK,
> .devtype = 0x00000013,
> }
> };
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 6591a59c1012..d8f047547a36 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -498,6 +498,48 @@
> ETM_MODE_EXCL_KERN | \
> ETM_MODE_EXCL_USER)
>
> +/*
> + * TRCDEVARCH Bit field definitions
> + * Bits[31:21] - ARCHITECT = Always Arm Ltd.
> + * * Bits[31:28] = 0x4
> + * * Bits[27:21] = 0b0111011
> + * Bit[20] - PRESENT, Indicates the presence of this register.
> + *
> + * Bit[19:16] - REVISION, Revision of the architecture.
> + *
> + * Bit[15:0] - ARCHID, Identifies this component as an ETM
> + * * Bits[15:12] - architecture version of ETM
> + * * = 4 for ETMv4
> + * * Bits[11:0] = 0xA13, architecture part number for ETM.
> + */
> +#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21)
> +#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21))
> +#define ETM_DEVARCH_PRESENT BIT(20)
> +#define ETM_DEVARCH_REVISION_SHIFT 16
> +#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16)
> +#define ETM_DEVARCH_REVISION(x) \
> + (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
> +#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0)
> +#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12
> +#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12)
> +#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \
> + (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
> +
> +#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \
> + (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
> +
> +#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL)
> +
> +#define ETM_DEVARCH_MAKE_ARCHID(major) \
> + ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
> +
> +#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4)
> +
> +#define ETM_DEVARCH_ID_MASK \
> + (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
> +#define ETM_DEVARCH_ETMv4x_ARCH \
> + (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
> +
> #define TRCSTATR_IDLE_BIT 0
> #define TRCSTATR_PMSTABLE_BIT 1
> #define ETM_DEFAULT_ADDR_COMP 0
> --
> 2.24.1
>
next prev parent reply other threads:[~2020-11-30 21:19 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 16:45 [PATCH v4 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-11-20 5:40 ` Sai Prakash Ranjan
2020-11-27 18:55 ` Mathieu Poirier
2020-11-30 9:37 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-11-27 19:11 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-11-30 20:55 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-11-30 21:04 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-11-30 21:19 ` Mathieu Poirier [this message]
2020-11-19 16:45 ` [PATCH v4 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-11-30 21:25 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-11-30 21:45 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-11-30 21:48 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-11-30 21:53 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-11-27 18:28 ` Mathieu Poirier
2020-11-30 9:30 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-11-30 22:42 ` Mathieu Poirier
2020-11-19 16:45 ` [PATCH v4 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-11-23 7:58 ` Tingwei Zhang
2020-11-23 9:39 ` Suzuki K Poulose
2020-11-24 0:41 ` Tingwei Zhang
2020-11-24 11:38 ` Suzuki K Poulose
2020-11-25 4:57 ` Tingwei Zhang
2020-11-19 16:45 ` [PATCH v4 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-11-19 17:18 ` Catalin Marinas
2020-11-20 10:03 ` Suzuki K Poulose
2020-11-19 16:45 ` [PATCH v4 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2020-11-19 17:22 ` Catalin Marinas
2020-11-20 10:03 ` Suzuki K Poulose
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