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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Apr 2021 15:50:28.8852 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32f82fb5-1aae-4b50-9db7-08d8f913b3e7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB2483 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ramakrishna Saripalli PSF mitigation introduces new kernel parameters. The kernel parameters for PSF mitigation are modeled after spec_store_bypass_disable. Signed-off-by: Ramakrishna Saripalli --- .../admin-guide/kernel-parameters.txt | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 04545725f187..68dfde77a87d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2876,6 +2876,7 @@ nospectre_v2 [X86,PPC,S390,ARM64] spectre_v2_user=off [X86] spec_store_bypass_disable=off [X86,PPC] + psfd=off [X86] ssbd=force-off [ARM64] l1tf=off [X86] mds=off [X86] @@ -3243,6 +3244,8 @@ nohugeiomap [KNL,X86,PPC,ARM64] Disable kernel huge I/O mappings. + nopsfd [HW,X86] Disable mitigation for Predictive Store Forwarding. + nosmt [KNL,S390] Disable symmetric multithreading (SMT). Equivalent to smt=1. @@ -4002,6 +4005,48 @@ that). Format: + psfd= [HW,X86] + Predictive Store Forwarding Disable control + + Certain AMD processors feature a new technology called Predictive + Store Forwarding. This feature is designed to improve the + performance of code execution by predicting dependencies + between loads and stores. + + Modern processors implement techniques to optimize the + execution of a load instruction to an address that was + recently written by a store instruction. + + PSF expands on the above by speculating on the relationship + between loads and stores without waiting for address + calculation to complete. With PSF, CPU learns over time the + relationship between loads and stores. + + Incorrect PSF predictions can occur for various reasons. + Please see the AMD PSF whitepaper for more information. + + All AMD processors that implement PSF also provide ability + to control mitigation of PSF. + + Following options are provided to control PSF mitigation. + + The options are: + on - Unconditionally disable Speculative Store Bypass + off - Unconditionally enable Speculative Store Bypass + auto - Kernel detects whether the CPU is vulnerable. + If the CPU is not vulnerable, off is selected. + If the CPU is vulnerable, default mitigation is + KConfig dependent. + prctl - Control Predictive Store Forwarding per thread + via prctl. Predictive Store Forwarding is enabled + per process by default. The state of the control + is inherited on fork. + seccomp - Same as prctl above but all seccomp threads will + disable PSF unless they opt out. + + Default mitigations: + [X86] If CONFIG_SECCOMP=y "seccomp" else "prctl" + psi= [KNL] Enable or disable pressure stall information tracking. Format: -- 2.25.1