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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id z9sm3554897oog.25.2021.06.01.10.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 10:45:21 -0700 (PDT) Received: (nullmailer pid 684833 invoked by uid 1000); Tue, 01 Jun 2021 17:45:19 -0000 Date: Tue, 1 Jun 2021 12:45:19 -0500 From: Rob Herring To: Pratyush Yadav Cc: Maxime Ripard , Mauro Carvalho Chehab , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Steve Longerbeam , Benoit Parrot , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, dmaengine@vger.kernel.org, Vignesh Raghavendra , Tomi Valkeinen , Chunfeng Yun , Laurent Pinchart Subject: Re: [PATCH v2 15/18] media: dt-bindings: Convert Cadence CSI2RX binding to YAML Message-ID: <20210601174519.GA666193@robh.at.kernel.org> References: <20210526152308.16525-1-p.yadav@ti.com> <20210526152308.16525-16-p.yadav@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210526152308.16525-16-p.yadav@ti.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 26, 2021 at 08:53:05PM +0530, Pratyush Yadav wrote: > Convert the Cadence CSI2RX binding to use YAML schema. > > Signed-off-by: Pratyush Yadav > > --- > > Changes in v2: > - New in v2. > > .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ----------- > .../bindings/media/cdns,csi2rx.yaml | 164 ++++++++++++++++++ > 2 files changed, 164 insertions(+), 100 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt > create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml > > diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt > deleted file mode 100644 > index 6b02a0657ad9..000000000000 > --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt > +++ /dev/null > @@ -1,100 +0,0 @@ > -Cadence MIPI-CSI2 RX controller > -=============================== > - > -The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI > -lanes in input, and 4 different pixel streams in output. > - > -Required properties: > - - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible > - - reg: base address and size of the memory mapped region > - - clocks: phandles to the clocks driving the controller > - - clock-names: must contain: > - * sys_clk: main clock > - * p_clk: register bank clock > - * pixel_if[0-3]_clk: pixel stream output clock, one for each stream > - implemented in hardware, between 0 and 3 > - > -Optional properties: > - - phys: phandle to the external D-PHY, phy-names must be provided > - - phy-names: must contain "dphy", if the implementation uses an > - external D-PHY > - > -Required subnodes: > - - ports: A ports node with one port child node per device input and output > - port, in accordance with the video interface bindings defined in > - Documentation/devicetree/bindings/media/video-interfaces.txt. The > - port nodes are numbered as follows: > - > - Port Description > - ----------------------------- > - 0 CSI-2 input > - 1 Stream 0 output > - 2 Stream 1 output > - 3 Stream 2 output > - 4 Stream 3 output > - > - The stream output port nodes are optional if they are not > - connected to anything at the hardware level or implemented > - in the design.Since there is only one endpoint per port, > - the endpoints are not numbered. > - > - > -Example: > - > -csi2rx: csi-bridge@0d060000 { > - compatible = "cdns,csi2rx"; > - reg = <0x0d060000 0x1000>; > - clocks = <&byteclock>, <&byteclock> > - <&coreclock>, <&coreclock>, > - <&coreclock>, <&coreclock>; > - clock-names = "sys_clk", "p_clk", > - "pixel_if0_clk", "pixel_if1_clk", > - "pixel_if2_clk", "pixel_if3_clk"; > - > - ports { > - #address-cells = <1>; > - #size-cells = <0>; > - > - port@0 { > - reg = <0>; > - > - csi2rx_in_sensor: endpoint { > - remote-endpoint = <&sensor_out_csi2rx>; > - clock-lanes = <0>; > - data-lanes = <1 2>; > - }; > - }; > - > - port@1 { > - reg = <1>; > - > - csi2rx_out_grabber0: endpoint { > - remote-endpoint = <&grabber0_in_csi2rx>; > - }; > - }; > - > - port@2 { > - reg = <2>; > - > - csi2rx_out_grabber1: endpoint { > - remote-endpoint = <&grabber1_in_csi2rx>; > - }; > - }; > - > - port@3 { > - reg = <3>; > - > - csi2rx_out_grabber2: endpoint { > - remote-endpoint = <&grabber2_in_csi2rx>; > - }; > - }; > - > - port@4 { > - reg = <4>; > - > - csi2rx_out_grabber3: endpoint { > - remote-endpoint = <&grabber3_in_csi2rx>; > - }; > - }; > - }; > -}; > diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml > new file mode 100644 > index 000000000000..ff5dd4211ac9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml > @@ -0,0 +1,164 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence MIPI-CSI2 RX controller > + > +description: | > + The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI > + lanes in input, and 4 different pixel streams in output. > + > +maintainers: > + - Pratyush Yadav > + > +properties: > + compatible: > + items: > + - const: cdns,csi2rx Since there has to be an SoC specific compatible, this should be: compatible: contains: const: cdns,csi2rx > + > + reg: > + maxItems: 1 > + > + clocks: > + minItems: 3 > + maxItems: 6 > + > + clock-names: > + minItems: 3 > + maxItems: 6 > + items: > + - const: sys_clk # main clock > + - const: p_clk # register bank clock > + - const: pixel_if0_clk # pixel stream 0 output clock > + - const: pixel_if1_clk # pixel stream 1 output clock > + - const: pixel_if2_clk # pixel stream 2 output clock > + - const: pixel_if3_clk # pixel stream 3 output clock > + > + phys: > + maxItems: 1 > + description: phandle to the external D-PHY > + > + phy-names: > + items: > + - const: dphy > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: CSI-2 input > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + clock-lanes: > + maxItems: 1 > + > + data-lanes: > + maxItems: 1 If there's only 1 lane, are you assigning between clock and data lanes? If not, then there's no mapping needed. > + > + required: > + - clock-lanes > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Stream 0 output > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: Stream 1 output > + > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: Stream 2 output > + > + port@4: > + $ref: /schemas/graph.yaml#/properties/port > + description: Stream 3 output > + > + required: > + - port@0 > + > + > +dependencies: > + phys: [ 'phy-names' ] > + phy-names: [ 'phys' ] > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + csi2rx: csi-bridge@d060000 { > + compatible = "cdns,csi2rx"; > + reg = <0x0d060000 0x1000>; > + clocks = <&byteclock>, <&byteclock>, > + <&coreclock>, <&coreclock>, > + <&coreclock>, <&coreclock>; > + clock-names = "sys_clk", "p_clk", > + "pixel_if0_clk", "pixel_if1_clk", > + "pixel_if2_clk", "pixel_if3_clk"; > + phys = <&dphy0>; > + phy-names = "dphy"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + csi2rx_in_sensor: endpoint { > + remote-endpoint = <&sensor_out_csi2rx>; > + clock-lanes = <0>; > + data-lanes = <1 2>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + csi2rx_out_grabber0: endpoint { > + remote-endpoint = <&grabber0_in_csi2rx>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + > + csi2rx_out_grabber1: endpoint { > + remote-endpoint = <&grabber1_in_csi2rx>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + > + csi2rx_out_grabber2: endpoint { > + remote-endpoint = <&grabber2_in_csi2rx>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + > + csi2rx_out_grabber3: endpoint { > + remote-endpoint = <&grabber3_in_csi2rx>; > + }; > + }; > + }; > + }; > -- > 2.30.0