From: Jisheng Zhang <jszhang3@mail.ustc.edu.cn>
To: Alexandre Ghiti <alex@ghiti.fr>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>,
Christoph Hellwig <hch@infradead.org>,
Zong Li <zong.li@sifive.com>, Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 2/4] riscv: Simplify xip and !xip kernel address conversion macros
Date: Fri, 4 Jun 2021 20:47:43 +0800 [thread overview]
Message-ID: <20210604204743.7bdd4fbd@xhacker> (raw)
In-Reply-To: <20210604114950.1446390-3-alex@ghiti.fr>
Hi Alexandre,
On Fri, 4 Jun 2021 13:49:48 +0200
Alexandre Ghiti <alex@ghiti.fr> wrote:
> To simplify the kernel address conversion code, make the same definition of
> kernel_mapping_pa_to_va and kernel_mapping_va_to_pa compatible for both xip
> and !xip kernel by defining XIP_OFFSET to 0 in !xip kernel.
>
> Signed-off-by: Alexandre Ghiti <alex@ghiti.fr>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> arch/riscv/include/asm/page.h | 14 +++-----------
> arch/riscv/include/asm/pgtable.h | 2 ++
> 2 files changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
> index 6a7761c86ec2..6e004d8fda4d 100644
> --- a/arch/riscv/include/asm/page.h
> +++ b/arch/riscv/include/asm/page.h
> @@ -93,9 +93,7 @@ extern unsigned long va_pa_offset;
> #ifdef CONFIG_64BIT
> extern unsigned long va_kernel_pa_offset;
> #endif
> -#ifdef CONFIG_XIP_KERNEL
> extern unsigned long va_kernel_xip_pa_offset;
> -#endif
> extern unsigned long pfn_base;
> #define ARCH_PFN_OFFSET (pfn_base)
> #else
> @@ -103,6 +101,7 @@ extern unsigned long pfn_base;
> #ifdef CONFIG_64BIT
> #define va_kernel_pa_offset 0
> #endif
> +#define va_kernel_xip_pa_offset 0
> #define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT)
> #endif /* CONFIG_MMU */
>
> @@ -110,29 +109,22 @@ extern unsigned long kernel_virt_addr;
>
> #ifdef CONFIG_64BIT
> #define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + va_pa_offset))
> -#ifdef CONFIG_XIP_KERNEL
> #define kernel_mapping_pa_to_va(y) ({ \
> unsigned long _y = y; \
> (_y >= CONFIG_PHYS_RAM_BASE) ? \
For !XIP, IIRC, one rule for riscv kernel is one unified Image for all RV64GC
or RV32GC platforms. When CONFIG_PHYS_RAM_BASE is available for all
riscv platforms after patch1, I'm not sure the common unified Image is still
possible or not.
One possible solution would be forcing CONFIG_PHYS_RAM_BASE = 0 if !XIP in patch1
or remove patch1 instead define CONFIG_PHY_RAM_BASE 0 for !XIP
Thanks
> (void *)((unsigned long)(_y) + va_kernel_pa_offset + XIP_OFFSET) : \
> (void *)((unsigned long)(_y) + va_kernel_xip_pa_offset); \
> })
> -#else
> -#define kernel_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + va_kernel_pa_offset))
> -#endif
> #define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x)
>
> #define linear_mapping_va_to_pa(x) ((unsigned long)(x) - va_pa_offset)
> -#ifdef CONFIG_XIP_KERNEL
> #define kernel_mapping_va_to_pa(y) ({ \
> unsigned long _y = y; \
> (_y < kernel_virt_addr + XIP_OFFSET) ? \
> ((unsigned long)(_y) - va_kernel_xip_pa_offset) : \
> ((unsigned long)(_y) - va_kernel_pa_offset - XIP_OFFSET); \
> })
> -#else
> -#define kernel_mapping_va_to_pa(x) ((unsigned long)(x) - va_kernel_pa_offset)
> -#endif
> +
> #define __va_to_pa_nodebug(x) ({ \
> unsigned long _x = x; \
> (_x < kernel_virt_addr) ? \
> @@ -141,7 +133,7 @@ extern unsigned long kernel_virt_addr;
> #else
> #define __pa_to_va_nodebug(x) ((void *)((unsigned long) (x) + va_pa_offset))
> #define __va_to_pa_nodebug(x) ((unsigned long)(x) - va_pa_offset)
> -#endif
> +#endif /* CONFIG_64BIT */
>
> #ifdef CONFIG_DEBUG_VIRTUAL
> extern phys_addr_t __virt_to_phys(unsigned long x);
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index bde8ce3bfe7c..d98e931a31e5 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -77,6 +77,8 @@
>
> #ifdef CONFIG_XIP_KERNEL
> #define XIP_OFFSET SZ_8M
> +#else
> +#define XIP_OFFSET 0
> #endif
>
> #ifndef __ASSEMBLY__
next prev parent reply other threads:[~2021-06-04 12:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-04 11:49 [PATCH v4 0/4] riscv: Map the kernel with correct permissions the first time Alexandre Ghiti
2021-06-04 11:49 ` [PATCH v4 1/4] riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED Alexandre Ghiti
2021-06-12 23:23 ` Emil Renner Berthing
2021-06-13 0:23 ` Palmer Dabbelt
2021-06-13 0:44 ` Jisheng Zhang
2021-06-13 6:14 ` Alex Ghiti
2021-06-04 11:49 ` [PATCH v4 2/4] riscv: Simplify xip and !xip kernel address conversion macros Alexandre Ghiti
2021-06-04 12:47 ` Jisheng Zhang [this message]
2021-06-06 7:38 ` Alex Ghiti
2021-06-04 11:49 ` [PATCH v4 3/4] riscv: Introduce set_kernel_memory helper Alexandre Ghiti
2021-06-04 11:49 ` [PATCH v4 4/4] riscv: Map the kernel with correct permissions the first time Alexandre Ghiti
2021-06-12 3:55 ` [PATCH v4 0/4] " Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210604204743.7bdd4fbd@xhacker \
--to=jszhang3@mail.ustc.edu.cn \
--cc=alex@ghiti.fr \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=hch@infradead.org \
--cc=jszhang@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=zong.li@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).