From: Apurva Nandan <a-nandan@ti.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
Patrice Chotard <patrice.chotard@foss.st.com>,
Boris Brezillon <boris.brezillon@collabora.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>
Cc: Apurva Nandan <a-nandan@ti.com>, Pratyush Yadav <p.yadav@ti.com>
Subject: [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash
Date: Tue, 13 Jul 2021 13:05:38 +0000 [thread overview]
Message-ID: <20210713130538.646-14-a-nandan@ti.com> (raw)
In-Reply-To: <20210713130538.646-1-a-nandan@ti.com>
Winbond W35N01JW is SPI NAND flash supporting Octal DTR SPI protocol.
Add op_vairants for W35N01JW, which include the Octal DTR read/write
page ops as well. Add W35N01JW's oob layout functions for the
mtd_ooblayout_ops. Add all op adjustments required for Octal DTR SPI
mode using the adjust_op(). Finally, add an entry for W35N01JW in
spinand_info table.
Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
---
drivers/mtd/nand/spi/winbond.c | 116 ++++++++++++++++++++++++++++++---
1 file changed, 107 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index 58cda07c15a0..5c2b9e61b624 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -16,6 +16,13 @@
#define WINBOND_CFG_BUF_READ BIT(3)
+#define WINBOND_BLK_ERASE_OPCODE 0xD8
+#define WINBOND_PAGE_READ_OPCODE 0x13
+#define WINBOND_PROG_EXEC_OPCODE 0x10
+#define WINBOND_READ_REG_OPCODE_1 0x05
+#define WINBOND_READ_REG_OPCODE_2 0x0F
+#define WINBOND_READ_VCR_OPCODE 0x85
+
/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/
#define WINBOND_IO_MODE_VCR_OCTAL_DTR 0xE7
#define WINBOND_IO_MODE_VCR_ADDR 0x00
@@ -24,7 +31,7 @@
#define WINBOND_DUMMY_CLK_COUNT 12
#define WINBOND_DUMMY_CLK_VCR_ADDR 0x01
-static SPINAND_OP_VARIANTS(read_cache_variants,
+static SPINAND_OP_VARIANTS(read_cache_variants_w25xxgv,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -32,14 +39,27 @@ static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-static SPINAND_OP_VARIANTS(write_cache_variants,
+static SPINAND_OP_VARIANTS(write_cache_variants_w25xxgv,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
-static SPINAND_OP_VARIANTS(update_cache_variants,
+static SPINAND_OP_VARIANTS(update_cache_variants_w25xxgv,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_w35n01jw,
+ SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(0, 24, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants_w35n01jw,
+ SPINAND_PROG_LOAD_OCTALIO_DTR(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants_w35n01jw,
+ SPINAND_PROG_LOAD_OCTALIO_DTR(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
@@ -64,11 +84,40 @@ static int w25m02gv_ooblayout_free(struct mtd_info *mtd, int section,
return 0;
}
+static int w35n01jw_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 7)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 12;
+ region->length = 4;
+
+ return 0;
+}
+
+static int w35n01jw_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 7)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 10;
+
+ return 0;
+}
+
static const struct mtd_ooblayout_ops w25m02gv_ooblayout = {
.ecc = w25m02gv_ooblayout_ecc,
.free = w25m02gv_ooblayout_free,
};
+static const struct mtd_ooblayout_ops w35n01jw_ooblayout = {
+ .ecc = w35n01jw_ooblayout_ecc,
+ .free = w35n01jw_ooblayout_free,
+};
+
static int w25m02gv_select_target(struct spinand_device *spinand,
unsigned int target)
{
@@ -88,9 +137,9 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w25xxgv,
+ &write_cache_variants_w25xxgv,
+ &update_cache_variants_w25xxgv),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
@@ -98,11 +147,22 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w25xxgv,
+ &write_cache_variants_w25xxgv,
+ &update_cache_variants_w25xxgv),
0,
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
+ SPINAND_INFO("W35N01JW",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdc),
+ NAND_MEMORG(1, 4096, 128, 64, 512, 20, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_w35n01jw,
+ &write_cache_variants_w35n01jw,
+ &update_cache_variants_w35n01jw),
+ SPINAND_HAS_OCTAL_DTR_BIT | SPINAND_HAS_POR_CMD_BIT |
+ SPINAND_HAS_CR_FEAT_BIT,
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)),
+
};
static int winbond_spinand_init(struct spinand_device *spinand)
@@ -183,9 +243,47 @@ static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand)
return 0;
}
+static void winbond_spinand_adjust_op(struct spi_mem_op *op,
+ const enum spinand_proto reg_proto)
+{
+ /*
+ * To support both 1 byte opcode and 2 byte opcodes, extract the MSB
+ * byte from the opcode as the LSB byte in 2 byte opcode is treated as
+ * don't care.
+ */
+ u8 opcode = op->cmd.opcode >> (8 * (op->cmd.nbytes - 1));
+
+ if (reg_proto == SPINAND_OCTAL_DTR) {
+ switch (opcode) {
+ case WINBOND_READ_REG_OPCODE_1:
+ case WINBOND_READ_REG_OPCODE_2:
+ op->dummy.nbytes = 14;
+ op->dummy.buswidth = 8;
+ op->dummy.dtr = true;
+ return;
+
+ case WINBOND_READ_VCR_OPCODE:
+ op->dummy.nbytes = 16;
+ op->dummy.buswidth = 8;
+ op->dummy.dtr = true;
+ return;
+
+ case WINBOND_BLK_ERASE_OPCODE:
+ case WINBOND_PAGE_READ_OPCODE:
+ case WINBOND_PROG_EXEC_OPCODE:
+ op->addr.nbytes = 2;
+ return;
+
+ default:
+ return;
+ }
+ }
+}
+
static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
.init = winbond_spinand_init,
.octal_dtr_enable = winbond_spinand_octal_dtr_enable,
+ .adjust_op = winbond_spinand_adjust_op,
};
const struct spinand_manufacturer winbond_spinand_manufacturer = {
--
2.17.1
next prev parent reply other threads:[~2021-07-13 13:07 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-13 13:05 [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Apurva Nandan
2021-07-13 13:05 ` [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Apurva Nandan
2021-07-14 17:06 ` Mark Brown
2021-08-23 7:57 ` Boris Brezillon
2021-07-13 13:05 ` [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Apurva Nandan
2021-07-13 13:05 ` [PATCH 03/13] mtd: spinand: Setup spi_mem_op for the SPI IO protocol using reg_proto Apurva Nandan
2021-08-06 18:30 ` Miquel Raynal
2021-08-20 9:52 ` Apurva Nandan
2021-08-20 12:08 ` Miquel Raynal
2021-08-23 7:11 ` Boris Brezillon
2021-08-23 7:24 ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 04/13] mtd: spinand: Fix odd byte addr and data phase in read/write reg op and write VCR op for Octal DTR mode Apurva Nandan
2021-08-06 18:43 ` Miquel Raynal
2021-08-20 10:27 ` Apurva Nandan
2021-08-20 12:06 ` Miquel Raynal
2021-07-13 13:05 ` [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Apurva Nandan
2021-07-13 13:05 ` [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Apurva Nandan
2021-08-06 18:54 ` Miquel Raynal
2021-08-20 10:35 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 07/13] mtd: spinand: Allow enabling Octal DTR mode in the core Apurva Nandan
2021-08-06 18:58 ` Miquel Raynal
2021-08-20 10:41 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Apurva Nandan
2021-08-06 19:01 ` Miquel Raynal
2021-08-20 11:26 ` Apurva Nandan
2021-08-20 12:14 ` Miquel Raynal
2021-08-20 13:54 ` Apurva Nandan
2021-08-20 14:38 ` Miquel Raynal
2021-08-20 15:53 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Apurva Nandan
2021-08-06 19:05 ` Miquel Raynal
2021-08-20 11:30 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond manufacturer_ops Apurva Nandan
2021-08-06 19:06 ` Miquel Raynal
2021-08-20 11:31 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 11/13] mtd: spinand: Add support for Power-on-Reset (PoR) instruction Apurva Nandan
2021-08-06 19:08 ` Miquel Raynal
2021-08-20 11:39 ` Apurva Nandan
2021-08-20 12:18 ` Miquel Raynal
2021-08-20 13:41 ` Apurva Nandan
2021-08-20 14:17 ` Miquel Raynal
2021-08-20 15:56 ` Apurva Nandan
2021-07-13 13:05 ` [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Apurva Nandan
2021-08-06 19:12 ` Miquel Raynal
2021-08-20 11:45 ` Apurva Nandan
2021-07-13 13:05 ` Apurva Nandan [this message]
2021-08-06 19:14 ` [PATCH 13/13] mtd: spinand: Add support for Winbond W35N01JW SPI NAND flash Miquel Raynal
2021-08-20 11:51 ` Apurva Nandan
2021-08-20 12:02 ` Miquel Raynal
2021-08-20 13:14 ` Apurva Nandan
2021-07-20 16:53 ` [PATCH 00/13] mtd: spinand: Add Octal DTR SPI (8D-8D-8D) mode support Nandan, Apurva
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