linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Bharat Bhushan <bbhushan2@marvell.com>
To: <will@kernel.org>, <mark.rutland@arm.com>, <robh+dt@kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<sgoutham@marvell.com>
Cc: Bharat Bhushan <bbhushan2@marvell.com>
Subject: [PATCH 0/4] cn10k DDR Performance monitor support
Date: Mon, 26 Jul 2021 14:40:23 +0530	[thread overview]
Message-ID: <20210726091027.798-1-bbhushan2@marvell.com> (raw)

This patch series adds DDR performance monitor support
on Marvell cn10k series of processor.

First patch adds device tree binding changes.
Second patch add basic support (without overflow and event
ownership). Third and fourth patch adds overflow and event
ownership respectively.

Seems like 4th patch can be merged in second patch,
For easy review it is currently separate

Bharat Bhushan (4):
  dt-bindings: perf: marvell: cn10k ddr performance monitor
  perf/marvell: ADD cn10k DDR PMU basic support
  perf/marvell: cn10k DDR perfmon event overflow handling
  perf/marvell: cn10k DDR perf event core ownership

 .../bindings/perf/marvell-cn10k-ddr.txt       |  15 +
 drivers/perf/Kconfig                          |   7 +
 drivers/perf/Makefile                         |   1 +
 drivers/perf/marvell_cn10k_ddr_pmu.c          | 766 ++++++++++++++++++
 include/linux/cpuhotplug.h                    |   1 +
 5 files changed, 790 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.txt
 create mode 100644 drivers/perf/marvell_cn10k_ddr_pmu.c

-- 
2.17.1


             reply	other threads:[~2021-07-26  9:10 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-26  9:10 Bharat Bhushan [this message]
2021-07-26  9:10 ` [PATCH 1/4] dt-bindings: perf: marvell: cn10k ddr performance monitor Bharat Bhushan
2021-07-29 23:29   ` Rob Herring
2021-08-03 11:38     ` [EXT] " Bharat Bhushan
2021-07-26  9:10 ` [PATCH 2/4] perf/marvell: ADD cn10k DDR PMU basic support Bharat Bhushan
2021-07-26  9:10 ` [PATCH 3/4] perf/marvell: cn10k DDR perfmon event overflow handling Bharat Bhushan
2021-07-26  9:10 ` [PATCH 4/4] perf/marvell: cn10k DDR perf event core ownership Bharat Bhushan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210726091027.798-1-bbhushan2@marvell.com \
    --to=bbhushan2@marvell.com \
    --cc=devicetree@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=robh+dt@kernel.org \
    --cc=sgoutham@marvell.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).