Re: [Patch v4 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh

[Rob Herring <robh@kernel.org>]

On Tue, Jul 27, 2021 at 11:25:12AM -0400, Thara Gopinath wrote:
> Add dt binding documentation to describe Qualcomm
> Limits Management Hardware node.
> 
> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
> ---
> 
> v3->v4:
> 	- Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it
> 	  a phandle pointing to the cpu node instead of a number as per
> 	  Rob Herring's review comments.
> 	- Added suffix -millicelsius to all temperature properties as per
> 	  Rob Herring's review comments.
> 	- Dropped unnecessary #includes in the example as pointed out by Bjorn.
> 	- Other minor fixes.
> 
>  .../devicetree/bindings/thermal/qcom-lmh.yaml | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> new file mode 100644
> index 000000000000..0978f458b9ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2021 Linaro Ltd.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Limits Management Hardware(LMh)
> +
> +maintainers:
> +  - Thara Gopinath <thara.gopinath@linaro.org>
> +
> +description:
> +  Limits Management Hardware(LMh) is a hardware infrastructure on some
> +  Qualcomm SoCs that can enforce temperature and current limits as
> +  programmed by software for certain IPs like CPU.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,sdm845-lmh
> +
> +  reg:
> +    items:
> +      - description: core registers
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  '#interrupt-cells':
> +    const: 1
> +
> +  interrupt-controller: true
> +
> +  qcom,lmh-cpu:
> +    description:
> +      phandle of the first cpu in the LMh cluster
> +    $ref: /schemas/types.yaml#/definitions/phandle

'cpus' property is the somewhat standard way to reference a cpu.

But you should already have cpu topology information, why do you need 
this?

> +
> +  qcom,lmh-temp-arm-millicelsius:
> +    description:
> +      An integer expressing temperature threshold at which the LMh thermal
> +      FSM is engaged.
> +    $ref: /schemas/types.yaml#/definitions/int32

Standard unit-suffixes already have a type.

> +
> +  qcom,lmh-temp-low-millicelsius:
> +    description:
> +      An integer expressing temperature threshold at which the state machine
> +      will attempt to remove frequency throttling.
> +    $ref: /schemas/types.yaml#/definitions/int32
> +
> +  qcom,lmh-temp-high-millicelsius:
> +    description:
> +      An integer expressing temperature threshold at which the state machine
> +      will attempt to throttle the frequency.
> +    $ref: /schemas/types.yaml#/definitions/int32
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - #interrupt-cells
> +  - interrupt-controller
> +  - qcom,lmh-cpu
> +  - qcom,lmh-temp-arm-millicelsius
> +  - qcom,lmh-temp-low-millicelsius
> +  - qcom,lmh-temp-high-millicelsius
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    lmh_cluster1: lmh@17d70800 {

Drop unused labels.

> +      compatible = "qcom,sdm845-lmh";
> +      reg = <0x17d70800 0x401>;

0x401 is an odd size...

> +      interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +      qcom,lmh-cpu = <&CPU4>;
> +      qcom,lmh-temp-arm-millicelsius = <65000>;
> +      qcom,lmh-temp-low-millicelsius = <94500>;
> +      qcom,lmh-temp-high-millicelsius = <95000>;
> +      interrupt-controller;
> +      #interrupt-cells = <1>;
> +    };
> +  - |

Seems like this is 1 example, not 2.

> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    lmh_cluster0: lmh@17d78800 {
> +      compatible = "qcom,sdm845-lmh";
> +      reg = <0x17d78800 0x401>;
> +      interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +      qcom,lmh-cpu = <&CPU0>;
> +      qcom,lmh-temp-arm-millicelsius = <65000>;
> +      qcom,lmh-temp-low-millicelsius = <94500>;
> +      qcom,lmh-temp-high-millicelsius = <95000>;
> +      interrupt-controller;
> +      #interrupt-cells = <1>;
> +    };
> +  - |
> -- 
> 2.25.1
> 
>