From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2540C4338F for ; Thu, 29 Jul 2021 22:35:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C43E760F6F for ; Thu, 29 Jul 2021 22:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235155AbhG2Wfp (ORCPT ); Thu, 29 Jul 2021 18:35:45 -0400 Received: from Galois.linutronix.de ([193.142.43.55]:49312 "EHLO galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233789AbhG2WfK (ORCPT ); Thu, 29 Jul 2021 18:35:10 -0400 Message-ID: <20210729222543.203905260@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1627598105; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=uZuaut2JpvGfn2gpCKX+rCbymLOSgSIekmfYPWe2CMk=; b=nqOaLIUOaTou1DdTA5UvWBfb6j3F1E4jjCsClod7GaYzSXZ4LA/RTex8nTet6F44vLEoPi P/wrf2wzvGC6kTvQO5rkJJl/kVPeuqhGHeBMORRTYYffUaVF6z9FALexoQo1Tpc+IXPNi6 lOFgbKV7fSj4cvLAfqUy0zClZk3Z49K6o62bIaRsyiQOQbs71sAQfEf5tSrRct7umuDii8 QfAXTpiptOzUFqOSL9SYWacCITKpmjIcWsQp/dBeVBhvnrOWXpNSn74YVuFugN+ElhkbKN uoJinNE56XZ6srDKlBLuU/XEt0FrJfh2giY/AXAgy+oNyLgTsLVIqD1DZuj3Gg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1627598105; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: references:references; bh=uZuaut2JpvGfn2gpCKX+rCbymLOSgSIekmfYPWe2CMk=; b=QlTuqPb25LezbZyhxPwNdR0kY61X5X2sJJGk373lsnIIUq02gvWjIcWoq38Ge2Yke+qGCq 3Mf6AI2iHqpBJbBg== Date: Thu, 29 Jul 2021 23:51:56 +0200 From: Thomas Gleixner To: LKML Cc: Alex Williamson , "Raj, Ashok" , "David S. Miller" , Bjorn Helgaas , linux-pci@vger.kernel.org, Kevin Tian , Marc Zyngier , Ingo Molnar , x86@kernel.org, linux-s390@vger.kernel.org, Niklas Schnelle , Gerald Schaefer , Heiko Carstens , Christian Borntraeger Subject: [patch V2 17/19] PCI/MSI: Cleanup msi_mask() References: <20210729215139.889204656@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-transfer-encoding: 8-bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org msi_mask() is calculating the possible mask bits for MSI per vector masking. Rename it to msi_multi_mask() and hand the MSI descriptor pointer into it to simplify the call sites. Signed-off-by: Thomas Gleixner --- V2: New patch --- drivers/pci/msi.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -129,14 +129,6 @@ void __weak arch_restore_msi_irqs(struct return default_restore_msi_irqs(dev); } -static inline __attribute_const__ u32 msi_mask(unsigned x) -{ - /* Don't shift by >= width of type */ - if (x >= 5) - return 0xffffffff; - return (1 << (1 << x)) - 1; -} - /* * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to * mask all MSI interrupts by clearing the MSI enable bit does not work @@ -211,6 +203,14 @@ static void msi_set_mask_bit(struct irq_ } } +static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc) +{ + /* Don't shift by >= width of type */ + if (desc->msi_attrib.multi_cap >= 5) + return 0xffffffff; + return (1 << (1 << desc->msi_attrib.multi_cap)) - 1; +} + /** * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts * @data: pointer to irqdata associated to that interrupt @@ -419,8 +419,7 @@ static void __pci_restore_msi_state(stru arch_restore_msi_irqs(dev); pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); - msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap), - entry->msi_mask); + msi_mask_irq(entry, msi_multi_mask(entry), entry->msi_mask); control &= ~PCI_MSI_FLAGS_QSIZE; control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE; pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); @@ -642,7 +641,7 @@ static int msi_capability_init(struct pc return -ENOMEM; /* All MSIs are unmasked by default; mask them all */ - mask = msi_mask(entry->msi_attrib.multi_cap); + mask = msi_multi_mask(entry); msi_mask_irq(entry, mask, mask); list_add_tail(&entry->list, dev_to_msi_list(&dev->dev)); @@ -938,7 +937,6 @@ EXPORT_SYMBOL(pci_msi_vec_count); static void pci_msi_shutdown(struct pci_dev *dev) { struct msi_desc *desc; - u32 mask; if (!pci_msi_enable || !dev || !dev->msi_enabled) return; @@ -951,8 +949,7 @@ static void pci_msi_shutdown(struct pci_ dev->msi_enabled = 0; /* Return the device with MSI unmasked as initial states */ - mask = msi_mask(desc->msi_attrib.multi_cap); - msi_mask_irq(desc, mask, 0); + msi_mask_irq(desc, msi_multi_mask(desc), 0); /* Restore dev->irq to its default pin-assertion IRQ */ dev->irq = desc->msi_attrib.default_irq;