From: Richard Fitzgerald <rf@opensource.cirrus.com>
To: <broonie@kernel.org>
Cc: <alsa-devel@alsa-project.org>, <patches@opensource.cirrus.com>,
<linux-kernel@vger.kernel.org>,
Richard Fitzgerald <rf@opensource.cirrus.com>
Subject: [PATCH 5/8] ASoC: cs42l42: Add PLL configuration for 44.1kHz/16-bit
Date: Thu, 5 Aug 2021 17:11:08 +0100 [thread overview]
Message-ID: <20210805161111.10410-5-rf@opensource.cirrus.com> (raw)
In-Reply-To: <20210805161111.10410-1-rf@opensource.cirrus.com>
44.1kHz 16-bit standard I2S gives a SCLK of 1.4112 MHz. Add
a PLL configuration for this.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
---
sound/soc/codecs/cs42l42.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/codecs/cs42l42.c b/sound/soc/codecs/cs42l42.c
index 99c022be94a6..6895f2fe9eb0 100644
--- a/sound/soc/codecs/cs42l42.c
+++ b/sound/soc/codecs/cs42l42.c
@@ -586,6 +586,7 @@ struct cs42l42_pll_params {
* Table 4-5 from the Datasheet
*/
static const struct cs42l42_pll_params pll_ratio_table[] = {
+ { 1411200, 0, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
{ 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
{ 2304000, 0, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2},
{ 2400000, 0, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
--
2.11.0
next prev parent reply other threads:[~2021-08-05 16:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 16:11 [PATCH 1/8] ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 2/8] ASoC: cs42l42: Fix LRCLK frame start edge Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 3/8] ASoC: cs42l42: Constrain sample rate to prevent illegal SCLK Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 4/8] ASoC: cs42l42: Fix mono playback Richard Fitzgerald
2021-08-05 16:11 ` Richard Fitzgerald [this message]
2021-08-05 16:11 ` [PATCH 6/8] ASoC: cs42l42: Validate dai_set_sysclk() frequency Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 7/8] ASoC: cs42l42: Assume 24-bit samples are in 32-bit slots Richard Fitzgerald
2021-08-05 16:11 ` [PATCH 8/8] ASoC: cs42l42: Update module authors Richard Fitzgerald
2021-08-06 0:45 ` [PATCH 1/8] ASoC: cs42l42: PLL must be running when changing MCLK_SRC_SEL Mark Brown
2021-08-06 0:47 ` Mark Brown
2021-08-06 0:56 ` Mark Brown
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