From: Bjorn Helgaas <helgaas@kernel.org>
To: Shanker R Donthineni <sdonthineni@nvidia.com>
Cc: Amey Narkhede <ameynarkhede03@gmail.com>,
Bjorn Helgaas <bhelgaas@google.com>,
alex.williamson@redhat.com,
Raphael Norwitz <raphael.norwitz@nutanix.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
kw@linux.com, Sinan Kaya <okaya@kernel.org>,
Len Brown <lenb@kernel.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH v15 7/9] PCI: Setup ACPI fwnode early and at the same time with OF
Date: Mon, 16 Aug 2021 12:07:32 -0500 [thread overview]
Message-ID: <20210816170732.GA2927693@bjorn-Precision-5520> (raw)
In-Reply-To: <63e0f64c-e51b-feb7-a193-c2999a280b80@nvidia.com>
On Sat, Aug 14, 2021 at 11:16:11AM -0500, Shanker R Donthineni wrote:
> Hi Bjorn,
>
> On 8/13/21 11:10 PM, Bjorn Helgaas wrote:
> >>>> diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
> >>>> index eaddbf701759..dae021322b3f 100644
> >>>> --- a/drivers/pci/pci-acpi.c
> >>>> +++ b/drivers/pci/pci-acpi.c
> >>>> @@ -952,7 +952,6 @@ static bool acpi_pci_bridge_d3(struct pci_dev *dev)
> >>>> return false;
> >>>>
> >>>> /* Assume D3 support if the bridge is power-manageable by ACPI. */
> >>>> - pci_set_acpi_fwnode(dev);
> >>>> adev = ACPI_COMPANION(&dev->dev);
> >>> I *think* the Root Port code farther down in this function is also now
> >>> unnecessary:
> >>>
> >>> acpi_pci_bridge_d3(...)
> >>> {
> >>> ...
> >>> root = pcie_find_root_port(dev);
> >>> adev = ACPI_COMPANION(&root->dev);
> >>> if (root == dev) {
> >>> /*
> >>> * It is possible that the ACPI companion is not yet bound
> >>> * for the root port so look it up manually here.
> >>> */
> >>> if (!adev && !pci_dev_is_added(root))
> >>> adev = acpi_pci_find_companion(&root->dev);
> >>> }
> >>>
> >>> Since we're now setting the ACPI_COMPANION for every pci_dev long
> >>> before we get here, I think this could now be simplified to something
> >>> like this:
> >>>
> >>> acpi_pci_bridge_d3(...)
> >>> {
> >>> if (!dev->is_hotplug_bridge)
> >>> return false;
> >>>
> >>> adev = ACPI_COMPANION(&dev->dev);
> >>> if (adev && acpi_device_power_manageable(adev))
> >>> return true;
> >>>
> >>> root = pcie_find_root_port(dev);
> >>> if (!root)
> >>> return false;
> >>>
> >>> adev = ACPI_COMPANION(&root->dev);
> >>> if (!adev)
> >>> return false;
> >>>
> >>> rc = acpi_dev_get_property(dev, "HotPlugSupportInD3",
> >>> ACPI_TYPE_INTEGER, &val);
> >>> if (rc < 0)
> >>> return false;
> >>>
> >>> return val == 1;
> >>> }
> >> Agree, thanks for your suggestion. Yes, it can be simplified too.
> >> Can I do something like this using the unified device property API?
> >>
> >> static bool acpi_pci_bridge_d3(struct pci_dev *dev)
> >> {
> >> struct acpi_device *adev;
> >> struct pci_dev *root;
> >> u8 val;
> >>
> >> if (!dev->is_hotplug_bridge)
> >> return false;
> >>
> >> adev = ACPI_COMPANION(&dev->dev);
> >> if (adev && acpi_device_power_manageable(adev))
> >> return true;
> >>
> >> root = pcie_find_root_port(dev);
> >> if (!root)
> >> return false;
> >>
> >> if (device_property_read_u8(&root->dev, "HotPlugSupportInD3", &val))
> >> return false;
> > I guess that might be OK.
> >
> > TBH I don't really like the device_property_read_u8() thing because
> > (1) we know this is an ACPI property and I don't see a reason to use
> > an "generic" interface that doesn't buy us anything, and (2) the
> > connection to the source of the data (a _DSD method) is really, really
> > hard to find.
> >
> > Admittedly, it's still pretty hard to connect acpi_dev_get_property()
> > with "_DSD". The only real clue is the comment about "Look for a
> > special _DSD property ..."
> >
> Does it satisfy you if I change the comment and still use device_property API?
>
> static bool acpi_pci_bridge_d3(struct pci_dev *dev)
> {
> struct pci_dev *rpdev;
> u8 val;
>
> if (!dev->is_hotplug_bridge)
> return false;
>
> /* Assume D3 support if the bridge is power-manageable by ACPI. */
> if (acpi_pci_power_manageable(dev))
> return true;
>
> /*
> * Look for 'HotPlugSupportInD3' property for the root port and if
> * it is set we know the hierarchy behind it supports D3 just fine.
> */
> rpdev = pcie_find_root_port(dev);
> if (!rpdev)
> return false;
>
> if (device_property_read_u8(&rpdev->dev, "HotPlugSupportInD3", &val))
> return false;
>
> return val == 1;
> }
>
> If not, I'll do changes like this.
I guess either one is fine. But I think we should extend the comment
and commit log to make it clear that device_property_read_u8() and
acpi_dev_get_property() are ultimately looking for a _DSD. I should
have asked for this when we merged 26ad34d510a8 ("PCI / ACPI:
Whitelist D3 for more PCIe hotplug ports") in the first place.
If we expect that power management *should* be enabled for a bridge,
and we observe that it *isn't* enabled, it is unreasonably difficult
to figure out from the code what is missing in the firmware, namely,
the _DSD laid out in the commit log for 26ad34d510a8.
> static bool acpi_pci_bridge_d3(struct pci_dev *dev)
> {
> const union acpi_object *obj;
> struct acpi_device *adev;
> struct pci_dev *rpdev;
>
>
> if (!dev->is_hotplug_bridge)
> return false;
>
> /* Assume D3 support if the bridge is power-manageable by ACPI. */
> if (acpi_pci_power_manageable(dev))
> return true;
>
> /*
> * Look for 'HotPlugSupportInD3' property for the root port and if
> * it is set we know the hierarchy behind it supports D3 just fine.
> */
> rpdev = pcie_find_root_port(dev);
> if (!rpdev)
> return false;
>
> adev = ACPI_COMPANION(&rpdev->dev);
> if (!adev)
> return false;
>
> if (acpi_dev_get_property(adev, "HotPlugSupportInD3",
> ACPI_TYPE_INTEGER, &obj) < 0)
> return false;
>
> return obj->integer.value == 1;
> }
>
>
next prev parent reply other threads:[~2021-08-16 17:07 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 16:29 [PATCH v15 0/9] PCI: Expose and manage PCI device reset Amey Narkhede
2021-08-05 16:29 ` [PATCH v15 1/9] PCI: Cache PCIe FLR capability Amey Narkhede
2021-08-09 11:13 ` Raphael Norwitz
2021-08-05 16:29 ` [PATCH v15 2/9] PCI: Add pcie_reset_flr to follow calling convention of other reset methods Amey Narkhede
2021-08-09 11:15 ` Raphael Norwitz
2021-08-05 16:29 ` [PATCH v15 3/9] PCI: Add new array for keeping track of ordering of " Amey Narkhede
2021-08-09 11:18 ` Raphael Norwitz
2021-08-05 16:29 ` [PATCH v15 4/9] PCI: Remove reset_fn field from pci_dev Amey Narkhede
2021-08-05 16:29 ` [PATCH v15 5/9] PCI: Allow userspace to query and set device reset mechanism Amey Narkhede
2021-08-09 11:23 ` Raphael Norwitz
2021-08-05 16:29 ` [PATCH v15 6/9] PCI: Define a function to set ACPI_COMPANION in pci_dev Amey Narkhede
2021-08-05 16:29 ` [PATCH v15 7/9] PCI: Setup ACPI fwnode early and at the same time with OF Amey Narkhede
2021-08-13 23:04 ` Bjorn Helgaas
2021-08-14 3:35 ` Shanker R Donthineni
2021-08-14 4:10 ` Bjorn Helgaas
2021-08-14 16:16 ` Shanker R Donthineni
2021-08-16 17:07 ` Bjorn Helgaas [this message]
2021-08-05 16:29 ` [PATCH v15 8/9] PCI: Add support for ACPI _RST reset method Amey Narkhede
2021-08-05 16:29 ` [PATCH v15 9/9] PCI: Change the type of probe argument in reset functions Amey Narkhede
2021-08-14 14:05 ` Shanker R Donthineni
2021-08-12 13:03 ` [PATCH v15 0/9] PCI: Expose and manage PCI device reset Shanker R Donthineni
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