From: Lai Jiangshan <jiangshanlai@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: Lai Jiangshan <laijs@linux.alibaba.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Youquan Song <youquan.song@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Tony Luck <tony.luck@intel.com>
Subject: [PATCH V2 16/41] x86/entry: Implement the whole error_entry() as C code
Date: Sun, 26 Sep 2021 23:08:13 +0800 [thread overview]
Message-ID: <20210926150838.197719-17-jiangshanlai@gmail.com> (raw)
In-Reply-To: <20210926150838.197719-1-jiangshanlai@gmail.com>
From: Lai Jiangshan <laijs@linux.alibaba.com>
All the needed facilities are set in entry64.c, the whole error_entry()
can be implemented in C in entry64.c. The C version generally has better
readability and easier to be updated/improved.
No function change intended. Only a check for X86_FEATURE_XENPV is added
because the new error_entry() does not use the pv SWAPGS, rather it uses
native_swapgs(). And for XENPV, error_entry() has nothing to do, so it
can return directly.
Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
---
arch/x86/entry/entry64.c | 76 ++++++++++++++++++++++++++++++++++
arch/x86/entry/entry_64.S | 80 +-----------------------------------
arch/x86/include/asm/traps.h | 1 +
3 files changed, 78 insertions(+), 79 deletions(-)
diff --git a/arch/x86/entry/entry64.c b/arch/x86/entry/entry64.c
index dafae60d31f9..5f2be4c3f333 100644
--- a/arch/x86/entry/entry64.c
+++ b/arch/x86/entry/entry64.c
@@ -56,3 +56,78 @@ static __always_inline void kernel_entry_fence_no_swapgs(void)
{
alternative("", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL);
}
+
+/*
+ * Put pt_regs onto the task stack and switch GS and CR3 if needed.
+ * The actual stack switch is done in entry_64.S.
+ *
+ * Becareful, it might be in the user CR3 and user GS base at the start
+ * of the function.
+ */
+asmlinkage __visible __entry_text
+struct pt_regs *error_entry(struct pt_regs *eregs)
+{
+ unsigned long iret_ip = (unsigned long)native_irq_return_iret;
+
+ asm volatile ("cld");
+
+ /*
+ * When XENPV, it is already in the task stack, and it can't fault
+ * from native_irq_return_iret and asm_load_gs_index_gs_change()
+ * since XENPV uses its own pvops for iret and load_gs_index, and
+ * also it doesn't use PTI. So it can directly return and
+ * native_swapgs() can be used in the following code.
+ */
+ if (static_cpu_has(X86_FEATURE_XENPV))
+ return eregs;
+
+ if (user_mode(eregs)) {
+ /*
+ * We entered from user mode.
+ * Switch to kernel gsbase and CR3.
+ */
+ user_entry_swapgs_and_fence();
+ switch_to_kernel_cr3();
+
+ /* Put pt_regs onto the task stack. */
+ return sync_regs(eregs);
+ }
+
+ /*
+ * There are two places in the kernel that can potentially fault with
+ * usergs. Handle them here. B stepping K8s sometimes report a
+ * truncated RIP for IRET exceptions returning to compat mode. Check
+ * for these here too.
+ */
+ if ((eregs->ip == iret_ip) || (eregs->ip == (unsigned int)iret_ip)) {
+ eregs->ip = iret_ip; /* Fix truncated RIP */
+
+ /*
+ * We came from an IRET to user mode, so we have user
+ * gsbase and CR3. Switch to kernel gsbase and CR3:
+ */
+ user_entry_swapgs_and_fence();
+ switch_to_kernel_cr3();
+
+ /*
+ * Pretend that the exception came from user mode: set up
+ * pt_regs as if we faulted immediately after IRET and put
+ * pt_regs onto the real task stack.
+ */
+ return sync_regs(fixup_bad_iret(eregs));
+ }
+
+ /*
+ * Hack: asm_load_gs_index_gs_change can fail with user gsbase.
+ * If this happens, fix up gsbase and proceed. We'll fix up the
+ * exception and land in asm_load_gs_index_gs_change's error
+ * handler with kernel gsbase.
+ */
+ if (eregs->ip == (unsigned long)asm_load_gs_index_gs_change)
+ user_entry_swapgs_and_fence();
+ else
+ kernel_entry_fence_no_swapgs();
+
+ /* Enter from kernel, don't move pt_regs */
+ return eregs;
+}
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 757e7155670e..169ee14cc2d6 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -325,6 +325,7 @@ SYM_CODE_END(ret_from_fork)
PUSH_AND_CLEAR_REGS
ENCODE_FRAME_POINTER
+ movq %rsp, %rdi
call error_entry
movq %rax, %rsp /* switch stack settled by sync_regs() */
ENCODE_FRAME_POINTER
@@ -964,85 +965,6 @@ SYM_CODE_START_LOCAL(paranoid_exit)
jmp restore_regs_and_return_to_kernel
SYM_CODE_END(paranoid_exit)
-/*
- * Save all registers in pt_regs, and switch GS if needed.
- */
-SYM_CODE_START_LOCAL(error_entry)
- UNWIND_HINT_FUNC
- cld
- testb $3, CS+8(%rsp)
- jz .Lerror_kernelspace
-
- /*
- * We entered from user mode or we're pretending to have entered
- * from user mode due to an IRET fault.
- */
- SWAPGS
- FENCE_SWAPGS_USER_ENTRY
- /* We have user CR3. Change to kernel CR3. */
- SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
-
- leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
-.Lerror_entry_from_usermode_after_swapgs:
- /* Put us onto the real thread stack. */
- call sync_regs
- ret
-
-.Lerror_entry_done_lfence:
- FENCE_SWAPGS_KERNEL_ENTRY
-.Lerror_entry_done:
- leaq 8(%rsp), %rax /* return pt_regs pointer */
- ret
-
- /*
- * There are two places in the kernel that can potentially fault with
- * usergs. Handle them here. B stepping K8s sometimes report a
- * truncated RIP for IRET exceptions returning to compat mode. Check
- * for these here too.
- */
-.Lerror_kernelspace:
- leaq native_irq_return_iret(%rip), %rcx
- cmpq %rcx, RIP+8(%rsp)
- je .Lerror_bad_iret
- movl %ecx, %eax /* zero extend */
- cmpq %rax, RIP+8(%rsp)
- je .Lbstep_iret
- cmpq $asm_load_gs_index_gs_change, RIP+8(%rsp)
- jne .Lerror_entry_done_lfence
-
- /*
- * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
- * gsbase and proceed. We'll fix up the exception and land in
- * .Lgs_change's error handler with kernel gsbase.
- */
- SWAPGS
- FENCE_SWAPGS_USER_ENTRY
- jmp .Lerror_entry_done
-
-.Lbstep_iret:
- /* Fix truncated RIP */
- movq %rcx, RIP+8(%rsp)
- /* fall through */
-
-.Lerror_bad_iret:
- /*
- * We came from an IRET to user mode, so we have user
- * gsbase and CR3. Switch to kernel gsbase and CR3:
- */
- SWAPGS
- FENCE_SWAPGS_USER_ENTRY
- SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
-
- /*
- * Pretend that the exception came from user mode: set up pt_regs
- * as if we faulted immediately after IRET.
- */
- leaq 8(%rsp), %rdi /* arg0 = pt_regs pointer */
- call fixup_bad_iret
- mov %rax, %rdi
- jmp .Lerror_entry_from_usermode_after_swapgs
-SYM_CODE_END(error_entry)
-
SYM_CODE_START_LOCAL(error_return)
UNWIND_HINT_REGS
DEBUG_ENTRY_ASSERT_IRQS_OFF
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
index 1cdd7e8bcba7..686461ac9803 100644
--- a/arch/x86/include/asm/traps.h
+++ b/arch/x86/include/asm/traps.h
@@ -14,6 +14,7 @@
asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs);
asmlinkage __visible notrace
struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs);
+asmlinkage __visible notrace struct pt_regs *error_entry(struct pt_regs *eregs);
void __init trap_init(void);
asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *eregs);
#endif
--
2.19.1.6.gb485710b
next prev parent reply other threads:[~2021-09-26 15:10 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-26 15:07 [PATCH V2 00/41] x86/entry/64: Convert a bunch of ASM entry code into C code Lai Jiangshan
2021-09-26 15:07 ` [PATCH V2 01/41] x86/entry: Fix swapgs fence Lai Jiangshan
2021-09-26 20:43 ` Thomas Gleixner
2021-09-27 1:10 ` Lai Jiangshan
2021-09-27 3:27 ` Lai Jiangshan
2021-09-27 7:50 ` Thomas Gleixner
2021-09-26 15:07 ` [PATCH V2 02/41] x86/traps: Remove stack-protector from traps.c Lai Jiangshan
2021-09-27 10:19 ` Borislav Petkov
2021-09-27 10:49 ` Lai Jiangshan
2021-09-27 11:01 ` Borislav Petkov
2021-09-27 14:38 ` Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 03/41] compiler_types.h: Add __noinstr_section() for noinstr Lai Jiangshan
2021-09-27 18:09 ` Kees Cook
2021-09-26 15:08 ` [PATCH V2 04/41] x86/entry: Introduce __entry_text for entry code written in C Lai Jiangshan
2021-09-30 11:49 ` Borislav Petkov
2021-09-26 15:08 ` [PATCH V2 05/41] x86/entry: Move PTI_USER_* to arch/x86/include/asm/processor-flags.h Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 06/41] x86: Mark __native_read_cr3() & native_write_cr3() as __always_inline Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 07/41] x86/traps: Move the declaration of native_irq_return_iret into proto.h Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 08/41] x86/entry: Add arch/x86/entry/entry64.c for C entry code Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 09/41] x86/entry: Expose the address of .Lgs_change to entry64.c Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 10/41] x86/entry: Add C verion of SWITCH_TO_KERNEL_CR3 as switch_to_kernel_cr3() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 11/41] x86/entry: Add C user_entry_swapgs_and_fence() and kernel_entry_fence_no_swapgs() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 12/41] x86/traps: Move pt_regs only in fixup_bad_iret() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 13/41] x86/entry: Switch the stack after error_entry() returns Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 14/41] x86/entry: move PUSH_AND_CLEAR_REGS out of error_entry Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 15/41] objtool: Allow .entry.text function using CLD instruction Lai Jiangshan
2021-09-26 15:08 ` Lai Jiangshan [this message]
2021-09-28 21:34 ` [PATCH V2 16/41] x86/entry: Implement the whole error_entry() as C code Brian Gerst
2021-09-29 8:45 ` Peter Zijlstra
2021-09-26 15:08 ` [PATCH V2 17/41] x86/entry: Make paranoid_exit() callable Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 18/41] x86/entry: Call paranoid_exit() in asm_exc_nmi() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 19/41] x86/entry: move PUSH_AND_CLEAR_REGS out of paranoid_entry Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 20/41] x86/entry: Add the C version ist_switch_to_kernel_cr3() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 21/41] x86/entry: Add the C version ist_restore_cr3() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 22/41] x86/entry: Add the C version get_percpu_base() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 23/41] x86/entry: Add the C version ist_switch_to_kernel_gsbase() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 24/41] x86/entry: Implement the C version ist_paranoid_entry() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 25/41] x86/entry: Implement the C version ist_paranoid_exit() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 26/41] x86/entry: Add a C macro to define the function body for IST in .entry.text Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 27/41] x86/mce: Remove stack protector from mce/core.c Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 28/41] x86/debug, mce: Use C entry code Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 29/41] x86/idtentry.h: Move the definitions *IDTENTRY_{MCE|DEBUG}* up Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 30/41] x86/nmi: Use DEFINE_IDTENTRY_NMI for nmi Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 31/41] x86/nmi: Remove stack protector from nmi.c Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 32/41] x86/nmi: Use C entry code Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 33/41] x86/entry: Add a C macro to define the function body for IST in .entry.text with an error code Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 34/41] x86/doublefault: Use C entry code Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 35/41] x86/sev: Add and use ist_vc_switch_off_ist() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 36/41] x86/sev: Remove stack protector from sev.c Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 37/41] x86/sev: Use C entry code Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 38/41] x86/entry: Remove ASM function paranoid_entry() and paranoid_exit() Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 39/41] x86/entry: Remove the unused ASM macros Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 40/41] x86/entry: Remove save_ret from PUSH_AND_CLEAR_REGS Lai Jiangshan
2021-09-26 15:08 ` [PATCH V2 41/41] x86/syscall/64: Move the checking for sysret to C code Lai Jiangshan
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