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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, maz@kernel.org,
	catalin.marinas@arm.com, mark.rutland@arm.com,
	james.morse@arm.com, anshuman.khandual@arm.com,
	leo.yan@linaro.org, mike.leach@linaro.org, will@kernel.org,
	lcherian@marvell.com, coresight@lists.linaro.org
Subject: Re: [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated
Date: Thu, 30 Sep 2021 11:54:21 -0600	[thread overview]
Message-ID: <20210930175421.GB3047827@p14s> (raw)
In-Reply-To: <20210921134121.2423546-4-suzuki.poulose@arm.com>

Hi Suzuki,

On Tue, Sep 21, 2021 at 02:41:07PM +0100, Suzuki K Poulose wrote:
> We collect the trace from the TRBE on FILL event from IRQ context
> and when via update_buffer(), when the event is stopped. Let us

s/"and when via"/"and via"

> consolidate how we calculate the trace generated into a helper.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Leo Yan <leo.yan@linaro.org>
> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-trbe.c | 48 ++++++++++++--------
>  1 file changed, 30 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 63f7edd5fd1f..063c4505a203 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -527,6 +527,30 @@ static enum trbe_fault_action trbe_get_fault_act(u64 trbsr)
>  	return TRBE_FAULT_ACT_SPURIOUS;
>  }
>  
> +static unsigned long trbe_get_trace_size(struct perf_output_handle *handle,
> +					 struct trbe_buf *buf,
> +					 bool wrap)

Stacking

> +{
> +	u64 write;
> +	u64 start_off, end_off;
> +
> +	/*
> +	 * If the TRBE has wrapped around the write pointer has
> +	 * wrapped and should be treated as limit.
> +	 */
> +	if (wrap)
> +		write = get_trbe_limit_pointer();
> +	else
> +		write = get_trbe_write_pointer();
> +
> +	end_off = write - buf->trbe_base;

In both arm_trbe_alloc_buffer() and trbe_handle_overflow() the base address is
acquired using get_trbe_base_pointer() but here it is referenced directly - any
reason for that?  It certainly makes reviewing this simple patch quite
difficult because I keep wondering if I am missing something subtle...  

> +	start_off = PERF_IDX2OFF(handle->head, buf);
> +
> +	if (WARN_ON_ONCE(end_off < start_off))
> +		return 0;
> +	return (end_off - start_off);
> +}
> +
>  static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
>  				   struct perf_event *event, void **pages,
>  				   int nr_pages, bool snapshot)
> @@ -588,9 +612,9 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>  	struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev);
>  	struct trbe_buf *buf = config;
>  	enum trbe_fault_action act;
> -	unsigned long size, offset;
> -	unsigned long write, base, status;
> +	unsigned long size, status;
>  	unsigned long flags;
> +	bool wrap = false;
>  
>  	WARN_ON(buf->cpudata != cpudata);
>  	WARN_ON(cpudata->cpu != smp_processor_id());
> @@ -630,8 +654,6 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>  	 * handle gets freed in etm_event_stop().
>  	 */
>  	trbe_drain_and_disable_local();
> -	write = get_trbe_write_pointer();
> -	base = get_trbe_base_pointer();
>  
>  	/* Check if there is a pending interrupt and handle it here */
>  	status = read_sysreg_s(SYS_TRBSR_EL1);
> @@ -655,20 +677,11 @@ static unsigned long arm_trbe_update_buffer(struct coresight_device *csdev,
>  			goto done;
>  		}
>  
> -		/*
> -		 * Otherwise, the buffer is full and the write pointer
> -		 * has reached base. Adjust this back to the Limit pointer
> -		 * for correct size. Also, mark the buffer truncated.
> -		 */
> -		write = get_trbe_limit_pointer();
>  		perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
> +		wrap = true;
>  	}
>  
> -	offset = write - base;
> -	if (WARN_ON_ONCE(offset < PERF_IDX2OFF(handle->head, buf)))
> -		size = 0;
> -	else
> -		size = offset - PERF_IDX2OFF(handle->head, buf);
> +	size = trbe_get_trace_size(handle, buf, wrap);
>  
>  done:
>  	local_irq_restore(flags);
> @@ -749,11 +762,10 @@ static int trbe_handle_overflow(struct perf_output_handle *handle)
>  {
>  	struct perf_event *event = handle->event;
>  	struct trbe_buf *buf = etm_perf_sink_config(handle);
> -	unsigned long offset, size;
> +	unsigned long size;
>  	struct etm_event_data *event_data;
>  
> -	offset = get_trbe_limit_pointer() - get_trbe_base_pointer();
> -	size = offset - PERF_IDX2OFF(handle->head, buf);
> +	size = trbe_get_trace_size(handle, buf, true);
>  	if (buf->snapshot)
>  		handle->head += size;
>  
> -- 
> 2.24.1
> 

  reply	other threads:[~2021-09-30 17:54 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-21 13:41 [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 01/17] coresight: trbe: Fix incorrect access of the sink specific data Suzuki K Poulose
2021-09-22  5:41   ` Anshuman Khandual
2021-09-30 17:57   ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 02/17] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-09-22  6:47   ` Anshuman Khandual
2021-10-05 16:46   ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 03/17] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-09-30 17:54   ` Mathieu Poirier [this message]
2021-10-01  8:36     ` Suzuki K Poulose
2021-10-01 15:15       ` Mathieu Poirier
2021-10-01 15:22         ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 04/17] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 05/17] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 06/17] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 07/17] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-09-22  6:57   ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 08/17] arm64: Add erratum detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 09/17] coresight: trbe: Workaround TRBE errata " Suzuki K Poulose
2021-09-23  6:13   ` Anshuman Khandual
2021-09-28 10:40     ` Suzuki K Poulose
2021-10-01  4:21       ` Anshuman Khandual
2021-10-01 17:15   ` Mathieu Poirier
2021-10-04  8:46     ` Suzuki K Poulose
2021-10-04 16:47       ` Mathieu Poirier
2021-09-21 13:41 ` [PATCH v2 10/17] arm64: Enable workaround for TRBE " Suzuki K Poulose
2021-09-22  7:23   ` Anshuman Khandual
2021-09-22  8:11     ` Suzuki K Poulose
2021-10-01  4:35       ` Anshuman Khandual
2021-10-07 16:09   ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-09-22  7:39   ` Anshuman Khandual
2021-09-22 12:03     ` Suzuki K Poulose
2021-10-01  4:38       ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 12/17] coresight: trbe: Add a helper to fetch cpudata from perf handle Suzuki K Poulose
2021-09-22  7:59   ` Anshuman Khandual
2021-10-04 17:42   ` Mathieu Poirier
2021-10-05 22:35     ` Suzuki K Poulose
2021-10-06 17:15       ` Mathieu Poirier
2021-10-07  9:18         ` Suzuki K Poulose
2021-09-21 13:41 ` [PATCH v2 13/17] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-09-22  9:51   ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 14/17] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-09-22  9:58   ` Anshuman Khandual
2021-09-22 10:16     ` Suzuki K Poulose
2021-10-01  4:40       ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range Suzuki K Poulose
2021-09-22 10:59   ` Anshuman Khandual
2021-10-07 16:10   ` Catalin Marinas
2021-09-21 13:41 ` [PATCH v2 16/17] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-09-23  3:15   ` Anshuman Khandual
2021-09-28 10:32     ` Suzuki K Poulose
2021-10-01  4:56       ` Anshuman Khandual
2021-09-21 13:41 ` [PATCH v2 17/17] arm64: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
2021-09-22 11:03   ` Anshuman Khandual
2021-10-07 16:11   ` Catalin Marinas
2021-10-05 17:04 ` [PATCH v2 00/17] arm64: Self-hosted trace related errata workarounds Mathieu Poirier
2021-10-08  7:32 ` Will Deacon
2021-10-08  9:25   ` Suzuki K Poulose
2021-10-08  9:52     ` Will Deacon
2021-10-08  9:57       ` Suzuki K Poulose

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