From: Lai Jiangshan <jiangshanlai@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Lai Jiangshan <laijs@linux.alibaba.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>
Subject: [PATCH V4 47/50] x86/entry: Remove ASM function paranoid_entry() and paranoid_exit()
Date: Tue, 26 Oct 2021 22:38:45 +0800 [thread overview]
Message-ID: <20211026143851.19481-3-jiangshanlai@gmail.com> (raw)
In-Reply-To: <20211026141420.17138-1-jiangshanlai@gmail.com>
From: Lai Jiangshan <laijs@linux.alibaba.com>
IST exceptions are changed to use C entry code which uses the C function
ist_paranoid_entry() and ist_paranoid_exit(). The ASM function
paranoid_entry() and paranoid_exit() are useless.
Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
---
arch/x86/entry/entry_64.S | 129 --------------------------------------
1 file changed, 129 deletions(-)
diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 48b4c320f5e7..19f3e642707b 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -847,135 +847,6 @@ SYM_CODE_START(xen_failsafe_callback)
SYM_CODE_END(xen_failsafe_callback)
#endif /* CONFIG_XEN_PV */
-/*
- * Save all registers in pt_regs. Return GSBASE related information
- * in EBX depending on the availability of the FSGSBASE instructions:
- *
- * FSGSBASE R/EBX
- * N 0 -> SWAPGS on exit
- * 1 -> no SWAPGS on exit
- *
- * Y GSBASE value at entry, must be restored in paranoid_exit
- */
-SYM_CODE_START_LOCAL(paranoid_entry)
- UNWIND_HINT_FUNC
-
- /*
- * Always stash CR3 in %r14. This value will be restored,
- * verbatim, at exit. Needed if paranoid_entry interrupted
- * another entry that already switched to the user CR3 value
- * but has not yet returned to userspace.
- *
- * This is also why CS (stashed in the "iret frame" by the
- * hardware at entry) can not be used: this may be a return
- * to kernel code, but with a user CR3 value.
- *
- * Switching CR3 does not depend on kernel GSBASE so it can
- * be done before switching to the kernel GSBASE. This is
- * required for FSGSBASE because the kernel GSBASE has to
- * be retrieved from a kernel internal table.
- */
- SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
-
- /*
- * Handling GSBASE depends on the availability of FSGSBASE.
- *
- * Without FSGSBASE the kernel enforces that negative GSBASE
- * values indicate kernel GSBASE. With FSGSBASE no assumptions
- * can be made about the GSBASE value when entering from user
- * space.
- */
- ALTERNATIVE "jmp .Lparanoid_entry_checkgs", "", X86_FEATURE_FSGSBASE
-
- /*
- * Read the current GSBASE and store it in %rbx unconditionally,
- * retrieve and set the current CPUs kernel GSBASE. The stored value
- * has to be restored in paranoid_exit unconditionally.
- *
- * The unconditional write to GS base below ensures that no subsequent
- * loads based on a mispredicted GS base can happen, therefore no LFENCE
- * is needed here.
- */
- SAVE_AND_SET_GSBASE scratch_reg=%rax save_reg=%rbx
- ret
-
-.Lparanoid_entry_checkgs:
- /* EBX = 1 -> kernel GSBASE active, no restore required */
- movl $1, %ebx
- /*
- * The kernel-enforced convention is a negative GSBASE indicates
- * a kernel value. No SWAPGS needed on entry and exit.
- */
- movl $MSR_GS_BASE, %ecx
- rdmsr
- testl %edx, %edx
- jns .Lparanoid_entry_swapgs
- FENCE_SWAPGS_KERNEL_ENTRY
- ret
-
-.Lparanoid_entry_swapgs:
- swapgs
-
- /*
- * The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
- * unconditional CR3 write, even in the PTI case. So do an lfence
- * to prevent GS speculation, regardless of whether PTI is enabled.
- */
- FENCE_SWAPGS_KERNEL_ENTRY
-
- /* EBX = 0 -> SWAPGS required on exit */
- xorl %ebx, %ebx
- ret
-SYM_CODE_END(paranoid_entry)
-
-/*
- * "Paranoid" exit path from exception stack. This is invoked
- * only on return from IST interrupts that came from kernel space.
- *
- * We may be returning to very strange contexts (e.g. very early
- * in syscall entry), so checking for preemption here would
- * be complicated. Fortunately, there's no good reason to try
- * to handle preemption here.
- *
- * R/EBX contains the GSBASE related information depending on the
- * availability of the FSGSBASE instructions:
- *
- * FSGSBASE R/EBX
- * N 0 -> SWAPGS on exit
- * 1 -> no SWAPGS on exit
- *
- * Y User space GSBASE, must be restored unconditionally
- */
-SYM_CODE_START_LOCAL(paranoid_exit)
- UNWIND_HINT_REGS offset=8
- /*
- * The order of operations is important. RESTORE_CR3 requires
- * kernel GSBASE.
- *
- * NB to anyone to try to optimize this code: this code does
- * not execute at all for exceptions from user mode. Those
- * exceptions go through error_exit instead.
- */
- RESTORE_CR3 scratch_reg=%rax save_reg=%r14
-
- /* Handle the three GSBASE cases */
- ALTERNATIVE "jmp .Lparanoid_exit_checkgs", "", X86_FEATURE_FSGSBASE
-
- /* With FSGSBASE enabled, unconditionally restore GSBASE */
- wrgsbase %rbx
- ret
-
-.Lparanoid_exit_checkgs:
- /* On non-FSGSBASE systems, conditionally do SWAPGS */
- testl %ebx, %ebx
- jnz .Lparanoid_exit_done
-
- /* We are returning to a context with user GSBASE */
- swapgs
-.Lparanoid_exit_done:
- ret
-SYM_CODE_END(paranoid_exit)
-
SYM_CODE_START_LOCAL(error_return)
UNWIND_HINT_REGS
DEBUG_ENTRY_ASSERT_IRQS_OFF
--
2.19.1.6.gb485710b
next prev parent reply other threads:[~2021-10-26 14:39 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 14:13 [PATCH V4 00/50] x86/entry/64: Convert a bunch of ASM entry code into C code Lai Jiangshan
2021-10-26 14:13 ` [PATCH V4 01/50] x86/entry: Add fence for kernel entry swapgs in paranoid_entry() Lai Jiangshan
2021-10-27 12:19 ` Borislav Petkov
2021-10-28 0:51 ` Lai Jiangshan
2021-10-26 14:13 ` [PATCH V4 02/50] x86/entry: Use the correct fence macro after swapgs in kernel CR3 Lai Jiangshan
2021-10-26 14:13 ` [PATCH V4 03/50] x86/traps: Remove stack-protector from traps.c Lai Jiangshan
2021-10-26 14:13 ` [PATCH V4 04/50] x86/xen: Add xenpv_restore_regs_and_return_to_usermode() Lai Jiangshan
2021-11-02 8:58 ` Borislav Petkov
2021-11-02 9:19 ` Lai Jiangshan
2021-11-02 9:49 ` Borislav Petkov
2021-11-02 11:22 ` H. Peter Anvin
2021-11-02 14:27 ` Borislav Petkov
2021-10-26 14:20 ` [PATCH V4 05/50] x86/entry: Use swapgs and native_iret directly in swapgs_restore_regs_and_return_to_usermode Lai Jiangshan
2021-10-26 14:20 ` [PATCH V4 06/50] compiler_types.h: Add __noinstr_section() for noinstr Lai Jiangshan
2021-10-26 14:24 ` Miguel Ojeda
2021-10-26 14:20 ` [PATCH V4 07/50] x86/entry: Introduce __entry_text for entry code written in C Lai Jiangshan
2021-10-26 14:20 ` [PATCH V4 08/50] x86/entry: Move PTI_USER_* to arch/x86/include/asm/processor-flags.h Lai Jiangshan
2021-10-26 14:20 ` [PATCH V4 09/50] x86: Remove unused kernel_to_user_p4dp() and user_to_kernel_p4dp() Lai Jiangshan
2021-10-26 14:20 ` [PATCH V4 10/50] x86: Replace PTI_PGTABLE_SWITCH_BIT with PTI_USER_PGTABLE_BIT Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 11/50] x86: Mark __native_read_cr3() & native_write_cr3() as __always_inline Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 12/50] x86/traps: Move the declaration of native_irq_return_iret into proto.h Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 13/50] x86/entry: Add arch/x86/entry/entry64.c for C entry code Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 14/50] x86/entry: Expose the address of .Lgs_change to entry64.c Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 15/50] x86/entry: Add C verion of SWITCH_TO_KERNEL_CR3 as switch_to_kernel_cr3() Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 16/50] x86/traps: Add fence_swapgs_{user,kernel}_entry() Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 17/50] x86/entry: Add C {user,kernel}_entry_swapgs_and_fence() Lai Jiangshan
2021-10-26 14:27 ` [PATCH V4 18/50] x86/traps: Move pt_regs only in fixup_bad_iret() Lai Jiangshan
2021-10-26 14:30 ` [PATCH V4 19/50] x86/entry: Switch the stack after error_entry() returns Lai Jiangshan
2021-10-26 14:30 ` [PATCH V4 20/50] x86/entry: move PUSH_AND_CLEAR_REGS out of error_entry Lai Jiangshan
2021-10-26 14:30 ` [PATCH V4 21/50] x86/entry: Move cld to the start of idtentry Lai Jiangshan
2021-10-26 14:30 ` [PATCH V4 22/50] x86/entry: Don't call error_entry for XENPV Lai Jiangshan
2021-10-26 14:30 ` [PATCH V4 23/50] x86/entry: Convert SWAPGS to swapgs in error_entry() Lai Jiangshan
2021-10-26 14:32 ` [PATCH V4 24/50] x86/entry: Implement the whole error_entry() as C code Lai Jiangshan
2021-10-26 14:32 ` [PATCH V4 25/50] x86/entry: Use idtentry macro for entry_INT80_compat Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 26/50] x86/entry: Convert SWAPGS to swapgs in entry_SYSENTER_compat() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 27/50] x86: Remove the definition of SWAPGS Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 28/50] x86/entry: Make paranoid_exit() callable Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 29/50] x86/entry: Call paranoid_exit() in asm_exc_nmi() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 30/50] x86/entry: move PUSH_AND_CLEAR_REGS out of paranoid_entry Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 31/50] x86/entry: Add the C version ist_switch_to_kernel_cr3() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 32/50] x86/entry: Skip CR3 write when the saved CR3 is kernel CR3 in RESTORE_CR3 Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 33/50] x86/entry: Add the C version ist_restore_cr3() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 34/50] x86/entry: Add the C version get_percpu_base() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 35/50] x86/entry: Add the C version ist_switch_to_kernel_gsbase() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 36/50] x86/entry: Implement the C version ist_paranoid_entry() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 37/50] x86/entry: Implement the C version ist_paranoid_exit() Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 38/50] x86/entry: Add a C macro to define the function body for IST in .entry.text Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 39/50] x86/debug, mce: Use C entry code Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 40/50] x86/idtentry.h: Move the definitions *IDTENTRY_{MCE|DEBUG}* up Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 41/50] x86/nmi: Use DEFINE_IDTENTRY_NMI for nmi Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 42/50] x86/nmi: Use C entry code Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 43/50] x86/entry: Add a C macro to define the function body for IST in .entry.text with an error code Lai Jiangshan
2021-10-26 14:34 ` [PATCH V4 44/50] x86/doublefault: Use C entry code Lai Jiangshan
2021-10-26 14:38 ` [PATCH V4 45/50] x86/sev: Add and use ist_vc_switch_off_ist() Lai Jiangshan
2021-10-26 14:38 ` [PATCH V4 46/50] x86/sev: Use C entry code Lai Jiangshan
2021-10-26 14:38 ` Lai Jiangshan [this message]
2021-10-26 14:38 ` [PATCH V4 48/50] x86/entry: Remove the unused ASM macros Lai Jiangshan
2021-10-26 14:38 ` [PATCH V4 49/50] x86/entry: Remove save_ret from PUSH_AND_CLEAR_REGS Lai Jiangshan
2021-10-26 14:38 ` [PATCH V4 50/50] x86/syscall/64: Move the checking for sysret to C code Lai Jiangshan
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