From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 632EFC433EF for ; Tue, 15 Feb 2022 12:11:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237539AbiBOMLV (ORCPT ); Tue, 15 Feb 2022 07:11:21 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232629AbiBOMLU (ORCPT ); Tue, 15 Feb 2022 07:11:20 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E47AF68EA; Tue, 15 Feb 2022 04:11:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644927066; x=1676463066; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=bvHEaZ2uSpy8y3b69ROVRV1b0rGK089uqW/KMJ+6S0E=; b=Pp9iUDi718wqnswlcyVor+N7Dyi3l1LNa4KpENcFCTjpVByfOINkw2Cz d4vgLkg2aWwQptB36jG8/2gjh84zvT6fHCmM81I/7rn0Yu/WIX7KirBc8 iu0Vf6AxJ3P3FgFq7mpMOQD/onTlDfNzp8HhJZ9F/QibfFxyFd3VEsMpx L/u3LUlK3vxZMd5U8lGTzyW3KIMSsTzoaNVfnNpvdDxTCDAnWaAJvvpED fQreunBlPN25RoRYLq34d2A0KCBizzaY0aVhE3N1keZod0b9KfQp7x5dh vIrdj6TrWIf+aWtcIJfnHrdd8F7Xv0J+395JFnixtmEuMrWg+BpjWarIF Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10258"; a="237742214" X-IronPort-AV: E=Sophos;i="5.88,370,1635231600"; d="scan'208";a="237742214" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 04:11:06 -0800 X-IronPort-AV: E=Sophos;i="5.88,370,1635231600"; d="scan'208";a="570794182" Received: from guptapa-mobl1.amr.corp.intel.com ([10.212.198.79]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 04:11:05 -0800 Date: Tue, 15 Feb 2022 04:11:03 -0800 From: Pawan Gupta To: Borislav Petkov Cc: Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andi Kleen , Tony Luck , linux-kernel@vger.kernel.org, antonio.gomez.iglesias@linux.intel.com, neelima.krishnan@intel.com, stable@vger.kernel.org Subject: Re: [PATCH] x86/tsx: Use MSR_TSX_CTRL to clear CPUID bits Message-ID: <20220215121103.vhb2lpoygxn3xywy@guptapa-mobl1.amr.corp.intel.com> References: <5bd785a1d6ea0b572250add0c6617b4504bc24d1.1644440311.git.pawan.kumar.gupta@linux.intel.com> <20220214224121.ilhu23cfjdyhvahk@guptapa-mobl1.amr.corp.intel.com> <20220215002014.mb7g4y3hfefmyozx@guptapa-mobl1.amr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 15.02.2022 11:24, Borislav Petkov wrote: >On Mon, Feb 14, 2022 at 04:20:14PM -0800, Pawan Gupta wrote: >> ... we are calling tsx_clear_cpuid() unconditionally. > >I know, that's why I asked... > >> > If those CPUs which support only disabling TSX through MSR_IA32_TSX_CTRL >> > but don't have MSR_TSX_FORCE_ABORT - if those CPUs set >> > X86_FEATURE_RTM_ALWAYS_ABORT too, then this should work. > >... this^^. > >IOW, what are you fixing here exactly? > >Let's look at the two callsites of tsx_clear_cpuid(): > >1. tsx_init: that will do something on X86_FEATURE_RTM_ALWAYS_ABORT CPUs. > >2. init_intel: that will get called when > > tsx_ctrl_state == TSX_CTRL_RTM_ALWAYS_ABORT > >But TSX_CTRL_RTM_ALWAYS_ABORT gets set only when >X86_FEATURE_RTM_ALWAYS_ABORT is set. I.e., the first case, in >tsx_init(). > >So, IIUC, you wanna fix the case where CPUs which set >X86_FEATURE_RTM_ALWAYS_ABORT but *don't* have MSR_TSX_FORCE_ABORT, those >CPUs should still disable TSX through MSR_IA32_TSX_CTRL. > >Correct? That is exactly what this patch is fixing. Please let me know if you have any questions. Thanks, Pawan