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From: ira.weiny@intel.com
To: Dan Williams <dan.j.williams@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Ben Widawsky <ben@bwidawsk.net>,
	linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: [PATCH V9 7/9] cxl/port: Introduce cxl_cdat_valid()
Date: Tue, 31 May 2022 08:26:30 -0700	[thread overview]
Message-ID: <20220531152632.1397976-8-ira.weiny@intel.com> (raw)
In-Reply-To: <20220531152632.1397976-1-ira.weiny@intel.com>

From: Ira Weiny <ira.weiny@intel.com>

The CDAT data is protected by a checksum and should be the proper
length.

Introduce cxl_cdat_valid() to validate the data.  While at it check and
store the sequence number.

Signed-off-by: Ira Weiny <ira.weiny@intel.com>

---
Changes from V8
	Move code to cxl/core/pci.c

Changes from V6
	Change name to cxl_cdat_valid() as this validates all the CDAT
		data not just the header
	Add error and debug prints

Changes from V5
	New patch, split out
	Update cdat_hdr_valid()
		Remove revision and cs field parsing
			There is no point in these
		Add seq check and debug print.
---
 drivers/cxl/cdat.h     |  2 ++
 drivers/cxl/core/pci.c | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h
index f5193a6a51fe..3d8945612511 100644
--- a/drivers/cxl/cdat.h
+++ b/drivers/cxl/cdat.h
@@ -90,10 +90,12 @@
  *
  * @table: cache of CDAT table
  * @length: length of cached CDAT table
+ * @seq: Last read Sequence number of the CDAT table
  */
 struct cxl_cdat {
 	void *table;
 	size_t length;
+	u32 seq;
 };
 
 #endif /* !__CXL_CDAT_H__ */
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 4c25a7d7abfd..bb370df1cb6c 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -534,6 +534,40 @@ static int cxl_cdat_get_length(struct cxl_port *port, size_t *length)
 	return rc;
 }
 
+static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat)
+{
+	u32 *table = cdat->table;
+	u8 *data8 = cdat->table;
+	u32 length, seq;
+	u8 check;
+	int i;
+
+	length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]);
+	if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) {
+		dev_err(dev, "Invalid length %u (%zu-%zu)\n", length,
+			CDAT_HEADER_LENGTH_BYTES, cdat->length);
+		return false;
+	}
+
+	for (check = 0, i = 0; i < length; i++)
+		check += data8[i];
+
+	dev_dbg(dev, "CDAT length %u CS %u\n", length, check);
+	if (check != 0) {
+		dev_err(dev, "Invalid checksum %u\n", check);
+		return false;
+	}
+
+	seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]);
+	/* Store the sequence for now. */
+	if (cdat->seq != seq) {
+		dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq);
+		cdat->seq = seq;
+	}
+
+	return true;
+}
+
 static int cxl_cdat_read_table(struct cxl_port *port,
 			       struct cxl_cdat *cdat)
 {
@@ -581,6 +615,8 @@ static int cxl_cdat_read_table(struct cxl_port *port,
 
 	} while (entry_handle != 0xFFFF);
 
+	if (!rc && !cxl_cdat_valid(&port->dev, cdat))
+		return -EIO;
 	return rc;
 }
 
-- 
2.35.1


  parent reply	other threads:[~2022-05-31 15:27 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-31 15:26 [PATCH V9 0/9] CXL: Read CDAT and DSMAS data ira.weiny
2022-05-31 15:26 ` [PATCH V9 1/9] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-05-31 17:00   ` [PATCH v9 " Davidlohr Bueso
2022-05-31 15:26 ` [PATCH V9 2/9] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-05-31 17:00   ` [PATCH v9 " Davidlohr Bueso
2022-05-31 15:26 ` [PATCH V9 3/9] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-05-31 17:25   ` [PATCH v9 " Davidlohr Bueso
2022-05-31 17:56     ` Davidlohr Bueso
2022-06-01  4:53       ` Ira Weiny
2022-06-01 13:59         ` Davidlohr Bueso
2022-06-01 16:55           ` Ira Weiny
2022-05-31 15:26 ` [PATCH V9 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-05-31 17:50   ` Ben Widawsky
2022-06-01 14:35     ` Jonathan Cameron
2022-06-01 23:01     ` Ira Weiny
2022-05-31 15:26 ` [PATCH V9 5/9] cxl/port: Find a DOE mailbox which supports CDAT ira.weiny
2022-05-31 17:57   ` Ben Widawsky
2022-06-01 22:03     ` Ira Weiny
2022-05-31 15:26 ` [PATCH V9 6/9] cxl/port: Read CDAT table ira.weiny
2022-06-01 15:35   ` Jonathan Cameron
2022-06-01 16:31     ` Jonathan Cameron
2022-06-02 18:31       ` Ira Weiny
2022-06-02 22:47         ` Ira Weiny
2022-06-06 14:49           ` Jonathan Cameron
2022-05-31 15:26 ` ira.weiny [this message]
2022-05-31 17:21   ` [PATCH V9 7/9] cxl/port: Introduce cxl_cdat_valid() Alison Schofield
2022-06-01 22:10     ` Ira Weiny
2022-05-31 15:26 ` [PATCH V9 8/9] cxl/port: Retry reading CDAT on failure ira.weiny
2022-05-31 17:07   ` Alison Schofield
2022-06-01  4:54     ` Ira Weiny
2022-05-31 19:30   ` [PATCH v9 " Davidlohr Bueso
2022-05-31 15:26 ` [PATCH V9 9/9] cxl/port: Parse out DSMAS data from CDAT table ira.weiny

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