Re: [PATCH 1/2] RISC-V: Cache SBI vendor values

From: Andrew Jones <ajones@ventanamicro.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: atishp@atishpatra.org, anup@brainfault.org, will@kernel.org,
	mark.rutland@arm.com, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Conor.Dooley@microchip.com, cmuellner@linux.com,
	samuel@sholland.org
Subject: Re: [PATCH 1/2] RISC-V: Cache SBI vendor values
Date: Wed, 5 Oct 2022 19:07:02 +0200	[thread overview]
Message-ID: <20221005170702.bsvjssvau6yv47ku@kamzik> (raw)
In-Reply-To: <20221004203724.1459763-2-heiko@sntech.de>

On Tue, Oct 04, 2022 at 10:37:23PM +0200, Heiko Stuebner wrote:
> sbi_get_mvendorid(), sbi_get_marchid() and sbi_get_mimpid() might get
> called multiple times, though the values of these CSRs should not change
> during the runtime of a specific machine.
> 
> So cache the values in the functions and prevent multiple ecalls
> to read these values.
> 
> Suggested-by: Atish Patra <atishp@atishpatra.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  arch/riscv/kernel/sbi.c | 21 ++++++++++++++++++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..5be8f90f325e 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -625,17 +625,32 @@ static inline long sbi_get_firmware_version(void)
>  
>  long sbi_get_mvendorid(void)
>  {
> -	return __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> +	static long id = -1;
> +
> +	if (id < 0)
> +		id = __sbi_base_ecall(SBI_EXT_BASE_GET_MVENDORID);
> +
> +	return id;
>  }
>  
>  long sbi_get_marchid(void)
>  {
> -	return __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);
> +	static long id = -1;
> +
> +	if (id < 0)
> +		id = __sbi_base_ecall(SBI_EXT_BASE_GET_MARCHID);

The marchid register will be negative for commercial architecture ids
because the MSB must be set.

> +
> +	return id;
>  }
>  
>  long sbi_get_mimpid(void)
>  {
> -	return __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);
> +	static long id = -1;
> +
> +	if (id < 0)
> +		id = __sbi_base_ecall(SBI_EXT_BASE_GET_MIMPID);

The spec says this register is "left to the provider" and may be
left-justified. I don't think we can be sure the MSB will not be set.

For both cases I guess we need an extra bit to determine if we've cached
or not

  static bool cached;
  static long id;

  if (!cached) {
     id = ecall();
     cached = true;
  }

  return id;

> +
> +	return id;
>  }
>  
>  static void sbi_send_cpumask_ipi(const struct cpumask *target)
> -- 
> 2.35.1
> 

Thanks,
drew