From: Andrew Jones <ajones@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>,
Anup Patel <apatel@ventanamicro.com>,
Atish Patra <atishp@rivosinc.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>
Subject: Re: [PATCH V2 14/21] irqchip/riscv-intc: Add ACPI support
Date: Mon, 20 Feb 2023 20:37:14 +0100 [thread overview]
Message-ID: <20230220193714.kuef6sfg7xmdyfty@orel> (raw)
In-Reply-To: <20230216182043.1946553-15-sunilvl@ventanamicro.com>
On Thu, Feb 16, 2023 at 11:50:36PM +0530, Sunil V L wrote:
> Add support for initializing the RISC-V INTC driver on ACPI
> platforms.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> drivers/irqchip/irq-riscv-intc.c | 78 +++++++++++++++++++++++++++-----
> 1 file changed, 66 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> index f229e3e66387..97a8db0fbc6c 100644
> --- a/drivers/irqchip/irq-riscv-intc.c
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -6,6 +6,7 @@
> */
>
> #define pr_fmt(fmt) "riscv-intc: " fmt
> +#include <linux/acpi.h>
> #include <linux/atomic.h>
> #include <linux/bits.h>
> #include <linux/cpu.h>
> @@ -112,6 +113,30 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
> return intc_domain->fwnode;
> }
>
> +static int __init riscv_intc_init_common(struct fwnode_handle *fn)
> +{
> + int rc;
> +
> + intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
> + &riscv_intc_domain_ops, NULL);
> + if (!intc_domain) {
> + pr_err("unable to add IRQ domain\n");
> + return -ENXIO;
> + }
> +
> + rc = set_handle_irq(&riscv_intc_irq);
> + if (rc) {
> + pr_err("failed to set irq handler\n");
> + return rc;
> + }
> +
> + riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
> +
> + pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
> +
> + return 0;
> +}
> +
> static int __init riscv_intc_init(struct device_node *node,
> struct device_node *parent)
> {
> @@ -133,24 +158,53 @@ static int __init riscv_intc_init(struct device_node *node,
> if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
> return 0;
>
> - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
> - &riscv_intc_domain_ops, NULL);
> - if (!intc_domain) {
> - pr_err("unable to add IRQ domain\n");
> - return -ENXIO;
> - }
> -
> - rc = set_handle_irq(&riscv_intc_irq);
> + rc = riscv_intc_init_common(of_node_to_fwnode(node));
> if (rc) {
> - pr_err("failed to set irq handler\n");
> + pr_err("failed to initialize INTC\n");
> return rc;
> }
>
> - riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
> + return 0;
> +}
>
> - pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
> +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
> +
> +#ifdef CONFIG_ACPI
> +
> +static int __init
> +riscv_intc_acpi_init(union acpi_subtable_headers *header,
> + const unsigned long end)
Please keep the function and its return type on the same line. We can go
to 100 chars.
> +{
> + int rc;
> + struct fwnode_handle *fn;
> + struct acpi_madt_rintc *rintc;
> +
> + rintc = (struct acpi_madt_rintc *)header;
> +
> + /*
> + * The ACPI MADT will have one INTC for each CPU (or HART)
> + * so riscv_intc_acpi_init() function will be called once
> + * for each INTC. We only do INTC initialization
> + * for the INTC belonging to the boot CPU (or boot HART).
> + */
> + if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id())
> + return 0;
> +
> + fn = irq_domain_alloc_named_fwnode("RISCV-INTC");
> + if (!fn) {
> + pr_err("unable to allocate INTC FW node\n");
> + return -ENOMEM;
> + }
> +
> + rc = riscv_intc_init_common(fn);
> + if (rc) {
> + pr_err("failed to initialize INTC\n");
> + return rc;
> + }
>
> return 0;
> }
>
> -IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
> +IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
> + ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init);
> +#endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-02-20 19:37 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 18:20 [PATCH V2 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-02-16 18:20 ` [PATCH V2 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-02-16 18:20 ` [PATCH V2 02/21] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-02-16 18:20 ` [PATCH V2 03/21] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-02-16 18:20 ` [PATCH V2 04/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-02-20 15:44 ` Andrew Jones
2023-02-24 9:00 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 05/21] ACPI: Kconfig: Enable ACPI_PROCESSOR for RISC-V Sunil V L
2023-02-20 16:05 ` Andrew Jones
2023-02-24 8:45 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 06/21] ACPI: OSL: Make should_use_kmap() 0 " Sunil V L
2023-02-16 18:20 ` [PATCH V2 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-02-20 16:10 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 08/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-02-20 16:36 ` Andrew Jones
2023-02-24 12:03 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 09/21] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-02-20 16:37 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 10/21] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-02-20 17:08 ` Andrew Jones
2023-02-24 16:50 ` Sunil V L
2023-02-24 17:06 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 11/21] RISC-V: ACPI: Add a function to retrieve the hartid Sunil V L
2023-02-20 17:34 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 12/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-02-20 17:45 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 13/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-02-20 17:54 ` Andrew Jones
2023-02-24 12:27 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 14/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-02-20 19:37 ` Andrew Jones [this message]
2023-02-24 12:29 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 15/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-02-20 19:47 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 16/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-02-20 19:51 ` Andrew Jones
2023-02-16 18:20 ` [PATCH V2 17/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-02-20 19:58 ` Andrew Jones
2023-02-24 12:33 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 18/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-02-20 20:07 ` Andrew Jones
2023-02-24 12:36 ` Sunil V L
2023-02-24 13:07 ` Andrew Jones
2023-02-24 14:44 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 19/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-02-20 20:09 ` Andrew Jones
2023-02-24 8:46 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 20/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-02-20 20:14 ` Andrew Jones
2023-02-24 12:38 ` Sunil V L
2023-02-16 18:20 ` [PATCH V2 21/21] Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter Sunil V L
2023-02-20 20:15 ` Andrew Jones
2023-02-24 12:37 ` Sunil V L
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230220193714.kuef6sfg7xmdyfty@orel \
--to=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=apatel@ventanamicro.com \
--cc=atishp@rivosinc.com \
--cc=conor.dooley@microchip.com \
--cc=corbet@lwn.net \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=rafael.j.wysocki@intel.com \
--cc=rafael@kernel.org \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).