From: Conor Dooley <conor@kernel.org>
To: Jisheng Zhang <jszhang@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/3] riscv: optimize memcpy/memmove/memset
Date: Mon, 29 Jan 2024 18:16:13 +0000 [thread overview]
Message-ID: <20240129-prelaw-tweet-ae59a90ded20@spud> (raw)
In-Reply-To: <20240128111013.2450-1-jszhang@kernel.org>
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On Sun, Jan 28, 2024 at 07:10:10PM +0800, Jisheng Zhang wrote:
> This series is to renew Matteo's "riscv: optimized mem* functions"
> sereies.
>
> Compared with Matteo's original series, Jisheng made below changes:
> 1. adopt Emil's change to fix boot failure when build with clang
> 2. add corresponding changes to purgatory
> 3. always build optimized string.c rather than only build when optimize
> for performance
> 4. implement unroll support when src & dst are both aligned to keep
> the same performance as assembly version. After disassembling, I found
> that the unroll version looks something like below, so it acchieves
> the "unroll" effect as asm version but in C programming language:
> ld t2,0(a5)
> ld t0,8(a5)
> ld t6,16(a5)
> ld t5,24(a5)
> ld t4,32(a5)
> ld t3,40(a5)
> ld t1,48(a5)
> ld a1,56(a5)
> sd t2,0(a6)
> sd t0,8(a6)
> sd t6,16(a6)
> sd t5,24(a6)
> sd t4,32(a6)
> sd t3,40(a6)
> sd t1,48(a6)
> sd a1,56(a6)
> And per my testing, unrolling more doesn't help performance, so
> the "c" version only unrolls by using 8 GP regs rather than 16
> ones as asm version.
> 5. Add proper __pi_memcpy and __pi___memcpy alias
> 6. more performance numbers.
>
> Per my benchmark with [1] on TH1520, CV1800B and JH7110 platforms,
> the unaligned medium memcpy performance is running about 3.5x ~ 8.6x
> speed of the unpatched versions's! Check patch1 for more details and
> performance numbers.
>
> Link:https://github.com/ARM-software/optimized-routines/blob/master/string/bench/memcpy.c [1]
>
> Here is the original cover letter msg from Matteo:
> Replace the assembly mem{cpy,move,set} with C equivalent.
>
> Try to access RAM with the largest bit width possible, but without
> doing unaligned accesses.
>
> A further improvement could be to use multiple read and writes as the
> assembly version was trying to do.
>
> Tested on a BeagleV Starlight with a SiFive U74 core, where the
> improvement is noticeable.
However, with allmodconfig it doesn't compile:
Redirect to /build/tmp.zzMIlhgQQo and /build/tmp.vxnoxu8G5e
Tree base:
0c526539d432 ("riscv: optimized memcpy")
Building the whole tree with the patch
../arch/riscv/lib/string.c:118:7: error: expected identifier or '('
../arch/riscv/lib/string.c:118:7: error: expected ')'
../arch/riscv/lib/string.c:143:7: error: expected identifier or '('
../arch/riscv/lib/string.c:143:7: error: expected ')'
../arch/riscv/lib/string.c:118:7: error: expected identifier or '('
../arch/riscv/lib/string.c:118:7: error: expected ')'
../arch/riscv/lib/string.c:143:7: error: expected identifier or '('
../arch/riscv/lib/string.c:143:7: error: expected ')'
Seems to be the case both with llvm and gcc.
Cheers,
Conor.
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next prev parent reply other threads:[~2024-01-29 18:16 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-28 11:10 [PATCH 0/3] riscv: optimize memcpy/memmove/memset Jisheng Zhang
2024-01-28 11:10 ` [PATCH 1/3] riscv: optimized memcpy Jisheng Zhang
2024-01-28 12:35 ` David Laight
2024-01-30 12:11 ` Nick Kossifidis
2024-01-28 11:10 ` [PATCH 2/3] riscv: optimized memmove Jisheng Zhang
2024-01-28 12:47 ` David Laight
2024-01-30 11:30 ` Jisheng Zhang
2024-01-30 11:51 ` David Laight
2024-01-30 11:39 ` Nick Kossifidis
2024-01-30 13:12 ` Jisheng Zhang
2024-01-30 16:52 ` Nick Kossifidis
2024-01-31 5:25 ` Jisheng Zhang
2024-01-31 9:13 ` Nick Kossifidis
2024-01-28 11:10 ` [PATCH 3/3] riscv: optimized memset Jisheng Zhang
2024-01-30 12:07 ` Nick Kossifidis
2024-01-30 13:25 ` Jisheng Zhang
2024-02-01 23:04 ` David Laight
2024-01-29 18:16 ` Conor Dooley [this message]
2024-01-30 2:28 ` [PATCH 0/3] riscv: optimize memcpy/memmove/memset Jisheng Zhang
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