From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1B97C432BE for ; Wed, 18 Aug 2021 21:04:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6B8061101 for ; Wed, 18 Aug 2021 21:04:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233973AbhHRVF0 convert rfc822-to-8bit (ORCPT ); Wed, 18 Aug 2021 17:05:26 -0400 Received: from mga14.intel.com ([192.55.52.115]:22657 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233378AbhHRVFY (ORCPT ); Wed, 18 Aug 2021 17:05:24 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10080"; a="216155443" X-IronPort-AV: E=Sophos;i="5.84,332,1620716400"; d="scan'208";a="216155443" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2021 14:04:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,332,1620716400"; d="scan'208";a="449905446" Received: from irsmsx605.ger.corp.intel.com ([163.33.146.138]) by fmsmga007.fm.intel.com with ESMTP; 18 Aug 2021 14:04:47 -0700 Received: from tjmaciei-mobl5.localnet (10.209.60.224) by IRSMSX605.ger.corp.intel.com (163.33.146.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.10; Wed, 18 Aug 2021 22:04:44 +0100 From: Thiago Macieira To: Borislav Petkov , "Bae, Chang Seok" CC: "Lutomirski, Andy" , "tglx@linutronix.de" , "mingo@kernel.org" , "x86@kernel.org" , "Brown, Len" , "Hansen, Dave" , "Liu, Jing2" , "Shankar, Ravi V" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v9 12/26] x86/fpu/xstate: Use feature disable (XFD) to protect dynamic user state Date: Wed, 18 Aug 2021 14:04:41 -0700 Message-ID: <3399412.qF98CnctbS@tjmaciei-mobl5> Organization: Intel Corporation In-Reply-To: References: <20210730145957.7927-1-chang.seok.bae@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [10.209.60.224] X-ClientProxiedBy: orsmsx605.amr.corp.intel.com (10.22.229.18) To IRSMSX605.ger.corp.intel.com (163.33.146.138) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wednesday, 18 August 2021 13:43:50 PDT Bae, Chang Seok wrote: > > Then our API needs improving. An app should be able to ask the kernel > > "Do you support AMX?" get a proper answer and act accordingly. > > Maybe I’m missing something, but I wonder what’s the difference from > reading XCR0. That assumes the kernel will always enable the bits in XCR0, like it is doing today and with your patch, because modifying it is a VM exit. But it's not the only possible solution. A future kernel could decide to leave some bits off and only enable upon request. That's how macOS/Darwin does its AVX512 support. -- Thiago Macieira - thiago.macieira (AT) intel.com Software Architect - Intel DPG Cloud Engineering