From: okukatla@codeaurora.org
To: Stephen Boyd <swboyd@chromium.org>
Cc: Andy Gross <agross@kernel.org>, Rob Herring <robh+dt@kernel.org>,
bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
evgreen@google.com, georgi.djakov@linaro.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
mdtipton@codeaurora.org, sibis@codeaurora.org,
saravanak@google.com, seansw@qti.qualcomm.com, elder@linaro.org,
linux-pm@vger.kernel.org, linux-arm-msm-owner@vger.kernel.org,
okukatla=codeaurora.org@codeaurora.org
Subject: Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
Date: Wed, 15 Sep 2021 11:56:19 +0530 [thread overview]
Message-ID: <36fe241f845a27b52509274d007948b1@codeaurora.org> (raw)
In-Reply-To: <749157bdb4613ae370adfb7ba055a2a9@codeaurora.org>
On 2021-09-15 10:35, okukatla@codeaurora.org wrote:
> On 2021-09-04 00:36, Stephen Boyd wrote:
>> Quoting Odelu Kukatla (2021-08-20 04:23:41)
>>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
>>> SoCs.
>>>
>>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>>> ---
>>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
>>> 1 file changed, 11 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 53a21d0..cf59b47 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -1848,6 +1848,17 @@
>>> };
>>> };
>>>
>>> + epss_l3: interconnect@18590000 {
>>> + compatible = "qcom,sc7280-epss-l3";
>>> + reg = <0 0x18590000 0 1000>,
>>
>> Is this supposed to be 0x1000?
>>
> No, This is 1000 or 0x3E8.
We have mapped only required registers for L3 scaling, 1000/0x3E8 is
suffice.
But i will update it to 0x1000 in next revision so that entire clock
domain region-0 is mapped.
>>> + <0 0x18591000 0 0x100>,
>>> + <0 0x18592000 0 0x100>,
>>> + <0 0x18593000 0 0x100>;
>>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc
>>> GCC_GPLL0>;
>>> + clock-names = "xo", "alternate";
>>> + #interconnect-cells = <1>;
>>> + };
>>> +
>>> cpufreq_hw: cpufreq@18591000 {
>>> compatible = "qcom,cpufreq-epss";
>>> reg = <0 0x18591100 0 0x900>,
>>> --
>>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>>> Forum,
>>> a Linux Foundation Collaborative Project
>>>
next prev parent reply other threads:[~2021-09-15 6:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 11:23 [v7 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-08-23 20:44 ` Rob Herring
2021-08-20 11:23 ` [v7 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-09-03 19:06 ` Stephen Boyd
2021-09-15 5:05 ` okukatla
2021-09-15 6:26 ` okukatla [this message]
2021-09-15 19:40 ` Stephen Boyd
2021-09-16 8:00 ` okukatla
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