From: "Luck, Tony" <tony.luck@intel.com>
To: Wei Huang <wei.huang2@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "bp@suse.de" <bp@suse.de>,
"yazen.ghannam@amd.com" <yazen.ghannam@amd.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>,
"smita.koralahallichannabasappa@amd.com"
<smita.koralahallichannabasappa@amd.com>
Subject: RE: [PATCH 1/1] x86/mce/amd: Add PPIN support for AMD MCE
Date: Wed, 11 Mar 2020 16:05:07 +0000 [thread overview]
Message-ID: <3908561D78D1C84285E8C5FCA982C28F7F59AA85@ORSMSX115.amr.corp.intel.com> (raw)
In-Reply-To: <20200311044409.2717587-1-wei.huang2@amd.com>
+ if ((val & 3UL) == 2UL)
+ set_cpu_cap(c, X86_FEATURE_PPIN);
You may have copied a bug of mine from upstream. We recently found
a system where the BIOS enabled PPIN and set the lock bit.
If that is possible on AMD, then you should just check for enabled at this
point. "if (val & 2UL)"
See this commit in TIP tree:
59b5809655bd ("x86/mce: Fix logic and comments around MSR_PPIN_CTL")
Otherwise looks fine:
Acked-by: Tony Luck <tony.luck@intel.com>
-Tony
next prev parent reply other threads:[~2020-03-11 16:05 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-11 4:44 [PATCH 1/1] x86/mce/amd: Add PPIN support for AMD MCE Wei Huang
2020-03-11 16:05 ` Luck, Tony [this message]
2020-03-16 18:08 ` Borislav Petkov
2020-03-16 19:20 ` Wei Huang
2020-03-19 20:14 ` Wei Huang
2020-03-19 20:21 ` Borislav Petkov
2020-03-19 20:58 ` Huang2, Wei
2020-03-19 21:09 ` Borislav Petkov
2020-03-19 21:44 ` Huang2, Wei
2020-03-19 21:56 ` Borislav Petkov
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