From: "Luck, Tony" <tony.luck@intel.com>
To: "Zhang, Cathy" <cathy.zhang@intel.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>
Cc: "pbonzini@redhat.com" <pbonzini@redhat.com>,
"Christopherson, Sean J" <sean.j.christopherson@intel.com>,
"vkuznets@redhat.com" <vkuznets@redhat.com>,
"wanpengli@tencent.com" <wanpengli@tencent.com>,
"jmattson@google.com" <jmattson@google.com>,
"joro@8bytes.org" <joro@8bytes.org>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"bp@alien8.de" <bp@alien8.de>, "hpa@zytor.com" <hpa@zytor.com>,
"ricardo.neri-calderon@linux.intel.com"
<ricardo.neri-calderon@linux.intel.com>,
"Park, Kyung Min" <kyung.min.park@intel.com>,
"jpoimboe@redhat.com" <jpoimboe@redhat.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"Hansen, Dave" <dave.hansen@intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>
Subject: RE: [PATCH v2 0/4] Expose new features for intel processor
Date: Tue, 7 Jul 2020 23:22:47 +0000 [thread overview]
Message-ID: <3908561D78D1C84285E8C5FCA982C28F7F68AC87@ORSMSX115.amr.corp.intel.com> (raw)
In-Reply-To: <1594088183-7187-1-git-send-email-cathy.zhang@intel.com>
>Cathy Zhang (2):
> x86: Expose SERIALIZE for supported cpuid
> x86: Expose TSX Suspend Load Address Tracking
Having separate patches for adding the X86_FEATURE bits
is fine (provides space in the commit log to document what each
is for). In this case it also preserves the "Author" of each.
But you should combine patches 3 & 4 into a single patch. Making
two patches to each add one bit to the KVM cpuid code just looks
like you are trying to inflate your patch count.
-Tony
prev parent reply other threads:[~2020-07-07 23:22 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-07 2:16 [PATCH v2 0/4] Expose new features for intel processor Cathy Zhang
2020-07-07 2:16 ` [PATCH v2 1/4] x86/cpufeatures: Add enumeration for SERIALIZE instruction Cathy Zhang
2020-07-07 16:36 ` Andy Lutomirski
2020-07-08 2:21 ` Ricardo Neri
2020-07-22 23:02 ` Thomas Gleixner
2020-07-24 2:03 ` Ricardo Neri
2020-08-18 7:14 ` Paolo Bonzini
2020-07-07 2:16 ` [PATCH v2 2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions Cathy Zhang
2020-07-07 2:36 ` Kyung Min Park
2020-07-07 9:40 ` Greg KH
2020-07-08 8:33 ` Zhang, Cathy
2020-07-07 2:16 ` [PATCH v2 3/4] x86: Expose SERIALIZE for supported cpuid Cathy Zhang
2020-07-14 3:00 ` Sean Christopherson
2020-07-14 22:42 ` Zhang, Cathy
2020-07-14 23:05 ` hpa
2020-07-15 0:03 ` Zhang, Cathy
2020-07-15 4:18 ` hpa
2020-07-07 2:16 ` [PATCH v2 4/4] x86: Expose TSX Suspend Load Address Tracking Cathy Zhang
2020-07-07 23:22 ` Luck, Tony [this message]
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