From: Dmitry Osipenko <digetx@gmail.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>,
thierry.reding@gmail.com, jonathanh@nvidia.com,
tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,
linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com
Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore
Date: Thu, 1 Aug 2019 13:53:53 +0300 [thread overview]
Message-ID: <3b55a112-42a6-212b-beea-10b64d5341d9@gmail.com> (raw)
In-Reply-To: <b5a58bfc-c777-886f-d902-f499ec38e2ae@nvidia.com>
01.08.2019 0:04, Sowjanya Komatineni пишет:
>
> On 7/31/19 4:11 AM, Dmitry Osipenko wrote:
>> 31.07.2019 3:20, Sowjanya Komatineni пишет:
>>> This patch adds support for saving OSC clock frequency and the
>>> drive-strength during OSC clock init and creates an API to restore
>>> OSC control register value from the saved context.
>>>
>>> This API is invoked by Tegra210 clock driver during system resume
>>> to restore the OSC clock settings.
>>>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/clk/tegra/clk-tegra-fixed.c | 15 +++++++++++++++
>>> drivers/clk/tegra/clk.h | 1 +
>>> 2 files changed, 16 insertions(+)
>>>
>>> diff --git a/drivers/clk/tegra/clk-tegra-fixed.c
>>> b/drivers/clk/tegra/clk-tegra-fixed.c
>>> index 8d91b2b191cf..7c6c8abfcde6 100644
>>> --- a/drivers/clk/tegra/clk-tegra-fixed.c
>>> +++ b/drivers/clk/tegra/clk-tegra-fixed.c
>>> @@ -17,6 +17,10 @@
>>> #define OSC_CTRL 0x50
>>> #define OSC_CTRL_OSC_FREQ_SHIFT 28
>>> #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
>>> +#define OSC_CTRL_MASK (0x3f2 | \
>>> + (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
>>> +
>>> +static u32 osc_ctrl_ctx;
>>> int __init tegra_osc_clk_init(void __iomem *clk_base, struct
>>> tegra_clk *clks,
>>> unsigned long *input_freqs, unsigned int num,
>>> @@ -29,6 +33,7 @@ int __init tegra_osc_clk_init(void __iomem
>>> *clk_base, struct tegra_clk *clks,
>>> unsigned osc_idx;
>>> val = readl_relaxed(clk_base + OSC_CTRL);
>>> + osc_ctrl_ctx = val & OSC_CTRL_MASK;
>>> osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
>>> if (osc_idx < num)
>>> @@ -96,3 +101,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk
>>> *tegra_clks)
>>> *dt_clk = clk;
>>> }
>>> }
>>> +
>>> +void tegra_clk_osc_resume(void __iomem *clk_base)
>>> +{
>>> + u32 val;
>>> +
>>> + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
>>> + val |= osc_ctrl_ctx;
>>> + writel_relaxed(val, clk_base + OSC_CTRL);
>> Why a full raw u32 OSC_CTRL value couldn't be simply saved and restored?
>
> Storing and restoring only required fields to avoid accidental
> misconfiguration.
>
> OSC_CTRL register has other bits (PLL_REF_DIV) which are configured by
> BR depending on OSC_FREQ and also setting PLL_REF_DIV while PLLS are in
> use is not safe.
I'm looking at the clk-driver sources and see that none of the Tegra
drivers ever change the OSC_CTRL configuration, T30/114 even have
#defines for the OSC_CTRL that are unused.
So, this leads to a question.. does any bootloader really ever change
the OSC_CTRL such that it differs after resume from suspend in
comparison to the value at the time of kernel's booting up?
next prev parent reply other threads:[~2019-08-01 10:54 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 0:20 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 02/20] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni
2019-07-31 10:49 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 04/20] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 05/20] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
2019-07-31 11:11 ` Dmitry Osipenko
2019-07-31 21:04 ` Sowjanya Komatineni
2019-08-01 10:53 ` Dmitry Osipenko [this message]
2019-08-01 18:06 ` Sowjanya Komatineni
2019-08-01 18:42 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni
2019-07-31 9:50 ` Dmitry Osipenko
2019-07-31 10:44 ` Dmitry Osipenko
2019-07-31 23:09 ` Sowjanya Komatineni
2019-08-01 17:58 ` Sowjanya Komatineni
2019-08-01 19:00 ` Dmitry Osipenko
2019-08-01 19:42 ` Sowjanya Komatineni
2019-08-01 20:17 ` Dmitry Osipenko
2019-08-01 20:31 ` Sowjanya Komatineni
2019-08-01 20:54 ` Dmitry Osipenko
2019-08-01 21:30 ` Sowjanya Komatineni
2019-08-01 23:19 ` Sowjanya Komatineni
2019-08-01 23:49 ` Sowjanya Komatineni
2019-08-02 12:38 ` Dmitry Osipenko
2019-08-02 18:33 ` Sowjanya Komatineni
2019-08-02 20:13 ` Dmitry Osipenko
2019-08-02 20:17 ` Dmitry Osipenko
2019-08-02 20:32 ` Sowjanya Komatineni
2019-08-02 21:15 ` Dmitry Osipenko
2019-08-02 21:18 ` Sowjanya Komatineni
2019-08-02 23:51 ` Sowjanya Komatineni
2019-08-03 10:33 ` Dmitry Osipenko
2019-08-03 17:01 ` Sowjanya Komatineni
2019-08-03 23:44 ` Sowjanya Komatineni
2019-08-04 12:24 ` Dmitry Osipenko
2019-08-04 12:31 ` Dmitry Osipenko
2019-08-02 12:32 ` Dmitry Osipenko
2019-08-02 18:43 ` Sowjanya Komatineni
2019-08-02 20:20 ` Dmitry Osipenko
2019-08-02 20:37 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 08/20] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni
2019-07-31 10:14 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 09/20] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni
2019-07-31 10:12 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 11/20] cpufreq: tegra124: " Sowjanya Komatineni
2019-07-31 10:23 ` Dmitry Osipenko
2019-07-31 11:14 ` Dmitry Osipenko
2019-07-31 21:05 ` Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 12/20] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 13/20] clk: tegra210: Add suspend and resume support Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 14/20] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 15/20] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-07-31 11:04 ` Dmitry Osipenko
2019-07-31 21:08 ` Sowjanya Komatineni
2019-08-01 10:43 ` Dmitry Osipenko
2019-08-01 17:56 ` Sowjanya Komatineni
2019-08-01 18:39 ` Dmitry Osipenko
2019-07-31 0:20 ` [PATCH v7 17/20] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 18/20] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 19/20] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni
2019-07-31 0:20 ` [PATCH v7 20/20] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni
2019-07-31 21:10 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni
2019-07-31 21:10 ` [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni
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