From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <mperttunen@nvidia.com>,
<gregkh@linuxfoundation.org>, <sboyd@kernel.org>,
<tglx@linutronix.de>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>
Cc: <allison@lohutok.net>, <pdeschrijver@nvidia.com>,
<pgaikwad@nvidia.com>, <mturquette@baylibre.com>,
<horms+renesas@verge.net.au>, <Jisheng.Zhang@synaptics.com>,
<krzk@kernel.org>, <arnd@arndb.de>, <spujar@nvidia.com>,
<josephl@nvidia.com>, <vidyas@nvidia.com>,
<daniel.lezcano@linaro.org>, <mmaddireddy@nvidia.com>,
<markz@nvidia.com>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <lgirdwood@gmail.com>,
<broonie@kernel.org>, <perex@perex.cz>, <tiwai@suse.com>,
<alexios.zavras@intel.com>, <alsa-devel@alsa-project.org>
Subject: Re: [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver
Date: Tue, 10 Dec 2019 08:53:42 -0800 [thread overview]
Message-ID: <3f1c9325-3017-62be-1e3b-82fd28540fdf@nvidia.com> (raw)
In-Reply-To: <49da77dc-b346-68eb-9ef8-42cfb3221489@nvidia.com>
On 12/9/19 3:03 PM, Sowjanya Komatineni wrote:
>
> On 12/9/19 12:46 PM, Sowjanya Komatineni wrote:
>>
>> On 12/9/19 12:12 PM, Dmitry Osipenko wrote:
>>> 08.12.2019 00:36, Sowjanya Komatineni пишет:
>>>> On 12/7/19 11:59 AM, Sowjanya Komatineni wrote:
>>>>> On 12/7/19 8:00 AM, Dmitry Osipenko wrote:
>>>>>> 07.12.2019 18:53, Dmitry Osipenko пишет:
>>>>>>> 07.12.2019 18:47, Dmitry Osipenko пишет:
>>>>>>>> 07.12.2019 17:28, Dmitry Osipenko пишет:
>>>>>>>>> 06.12.2019 05:48, Sowjanya Komatineni пишет:
>>>>>>>>>> Tegra210 and prior Tegra PMC has clk_out_1, clk_out_2, clk_out_3
>>>>>>>>>> with
>>>>>>>>>> mux and gate for each of these clocks.
>>>>>>>>>>
>>>>>>>>>> Currently these PMC clocks are registered by Tegra clock driver
>>>>>>>>>> using
>>>>>>>>>> clk_register_mux and clk_register_gate by passing PMC base
>>>>>>>>>> address
>>>>>>>>>> and register offsets and PMC programming for these clocks
>>>>>>>>>> happens
>>>>>>>>>> through direct PMC access by the clock driver.
>>>>>>>>>>
>>>>>>>>>> With this, when PMC is in secure mode any direct PMC access
>>>>>>>>>> from the
>>>>>>>>>> non-secure world does not go through and these clocks will
>>>>>>>>>> not be
>>>>>>>>>> functional.
>>>>>>>>>>
>>>>>>>>>> This patch adds these clocks registration with PMC as a clock
>>>>>>>>>> provider
>>>>>>>>>> for these clocks. clk_ops callback implementations for these
>>>>>>>>>> clocks
>>>>>>>>>> uses tegra_pmc_readl and tegra_pmc_writel which supports PMC
>>>>>>>>>> programming
>>>>>>>>>> in secure mode and non-secure mode.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>> ---
>>>>>>>> [snip]
>>>>>>>>
>>>>>>>>>> +
>>>>>>>>>> +static const struct clk_ops pmc_clk_gate_ops = {
>>>>>>>>>> + .is_enabled = pmc_clk_is_enabled,
>>>>>>>>>> + .enable = pmc_clk_enable,
>>>>>>>>>> + .disable = pmc_clk_disable,
>>>>>>>>>> +};
>>>>>>>>> What's the benefit of separating GATE from the MUX?
>>>>>>>>>
>>>>>>>>> I think it could be a single clock.
>>>>>>>> According to TRM:
>>>>>>>>
>>>>>>>> 1. GATE and MUX are separate entities.
>>>>>>>>
>>>>>>>> 2. GATE is the parent of MUX (see PMC's CLK_OUT paths diagram
>>>>>>>> in TRM).
>>>>>>>>
>>>>>>>> 3. PMC doesn't gate EXTPERIPH clock but could "force-enable" it,
>>>>>>>> correct?
>>>> Was following existing clk-tegra-pmc as I am not sure of reason for
>>>> having these clocks registered as separate mux and gate clocks.
>>>>
>>>> Yes, PMC clocks can be registered as single clock and can use clk_ops
>>>> for set/get parent and enable/disable.
>>>>
>>>> enable/disable of PMC clocks is for force-enable to force the clock to
>>>> run regardless of ACCEPT_REQ or INVERT_REQ.
>>>>
>>>>>>> 4. clk_m_div2/4 are internal PMC OSC dividers and thus these clocks
>>>>>>> should belong to PMC.
>>>>>> Also, it should be "osc" and not "clk_m".
>>>>> I followed the same parents as it were in existing clk-tegra-pmc
>>>>> driver.
>>>>>
>>>>> Yeah they are wrong and they should be from osc and not clk_m.
>>>>>
>>>>> Will fix in next version.
>>>>>
> Reg clk_m_div2/3, they are dividers at OSC pad and not really internal
> to PMC block.
>
> current clock driver creates clk_m_div clocks which should actually be
> osc_div2/osc_div4 clocks with osc as parent.
>
> There are no clk_m_div2 and clk_m_div4 from clk_m
>
> Will fix this in next version.
>
>>> Could you please describe the full EXTPERIPH clock topology and how the
>>> pinmux configuration is related to it all?
>>>
>>> What is internal to the Tegra chip and what are the external outputs?
>>>
>>> Is it possible to bypass PMC on T30+ for the EXTPERIPH clocks?
>>
>> PMC CLK1/2/3 possible sources are OSC_DIV1, OSC_DIV2, OSC_DIV4,
>> EXTPERIPH from CAR.
>>
>> OSC_DIV1/2/4 are with internal dividers at the OSC Pads
>>
>> EXTPERIPH is from CAR and it has reset and enable controls along with
>> clock source selections to choose one of the PLLA_OUT0, CLK_S,
>> PLLP_OUT0, CLK_M, PLLE_OUT0
>>
>> So, PMC CLK1/2/4 possible parents are OSC_DIV1, OSC_DIV2, OSC_DIV4,
>> EXTERN.
>>
>>
>> CLK1/2/3 also has Pinmux to route EXTPERIPH output on to these pins.
>>
>>
>> When EXTERN output clock is selected for these PMC clocks thru
>> CLKx_SRC_SEL, output clock is from driver by EXTPERIPH from CAR via
>> Pinmux logic or driven as per CLKx_SRC_SEL bypassing pinmux based on
>> CLKx_ACCEPT_REQ bit.
>>
>>
>> PMC Clock control register has bit CLKx_ACCEPT_REQ
>> When CLKx_ACCEPT_REQ = 0, output clock driver is from by EXTPERIPH
>> through the pinmux
>> When CLKx_ACCEPT_REQ = 1, output clock is based on CLKx_SRC_SEL bits
>> (OSC_DIV1/2/4 and EXTPERIPH clock bypassing the pinmux)
>>
>> FORCE_EN bit in PMC CLock control register forces the clock to run
>> regardless of this.
PMC clock gate is based on the state of CLKx_ACCEPT_REQ and FORCE_EN
like explained above.
CLKx_ACCEPT_REQ is 0 default and FORCE_EN acts as gate to enable/disable
EXTPERIPH clock output to PMC CLK_OUT_1/2/3.
So I believe we need to register as MUX and Gate rather than as a single
clock. Please confirm.
next prev parent reply other threads:[~2019-12-10 16:53 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-06 2:48 [PATCH v3 00/15] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 01/15] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni
2019-12-06 18:58 ` Michał Mirosław
2019-12-06 2:48 ` [PATCH v3 02/15] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 03/15] soc: tegra: Add Tegra PMC clock registrations into PMC driver Sowjanya Komatineni
2019-12-07 14:28 ` Dmitry Osipenko
2019-12-07 15:47 ` Dmitry Osipenko
2019-12-07 15:53 ` Dmitry Osipenko
2019-12-07 16:00 ` Dmitry Osipenko
2019-12-07 19:59 ` Sowjanya Komatineni
2019-12-07 21:36 ` Sowjanya Komatineni
2019-12-09 20:12 ` Dmitry Osipenko
2019-12-09 20:46 ` Sowjanya Komatineni
2019-12-09 23:03 ` Sowjanya Komatineni
2019-12-10 16:53 ` Sowjanya Komatineni [this message]
2019-12-10 17:41 ` Dmitry Osipenko
2019-12-11 1:06 ` Sowjanya Komatineni
2019-12-11 18:50 ` Sowjanya Komatineni
2019-12-12 1:39 ` Dmitry Osipenko
2019-12-12 3:45 ` Sowjanya Komatineni
2019-12-12 3:54 ` Sowjanya Komatineni
2019-12-12 22:13 ` Dmitry Osipenko
2019-12-11 15:10 ` Peter De Schrijver
2019-12-12 1:43 ` Dmitry Osipenko
2019-12-16 12:20 ` Peter De Schrijver
2019-12-16 14:23 ` Dmitry Osipenko
2019-12-16 15:11 ` Peter De Schrijver
2019-12-16 15:24 ` Peter De Schrijver
2019-12-16 15:49 ` Dmitry Osipenko
2019-12-10 17:41 ` Dmitry Osipenko
[not found] ` <22a2f8bd-561d-f4c6-4eef-bb61095c53b2@nvidia.com>
2019-12-10 18:30 ` Dmitry Osipenko
2019-12-10 19:18 ` Sowjanya Komatineni
2019-12-10 20:31 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 04/15] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC blink control Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 05/15] soc: pmc: Add blink output clock registration to Tegra PMC Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 06/15] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Sowjanya Komatineni
2019-12-07 14:33 ` Dmitry Osipenko
2019-12-07 14:43 ` Dmitry Osipenko
2019-12-07 15:04 ` Dmitry Osipenko
2019-12-07 19:35 ` Sowjanya Komatineni
2019-12-07 23:24 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 07/15] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 08/15] ASoC: tegra: Add audio mclk control through clk_out_1 and extern1 Sowjanya Komatineni
2019-12-07 14:58 ` Dmitry Osipenko
2019-12-07 19:20 ` Sowjanya Komatineni
2019-12-09 20:06 ` Dmitry Osipenko
2019-12-09 23:05 ` Sowjanya Komatineni
2019-12-09 23:12 ` Dmitry Osipenko
2019-12-10 0:54 ` Sowjanya Komatineni
2019-12-17 1:29 ` Sowjanya Komatineni
2019-12-17 15:36 ` Dmitry Osipenko
2019-12-17 16:12 ` Sowjanya Komatineni
2019-12-17 16:16 ` Dmitry Osipenko
2019-12-17 16:39 ` Sowjanya Komatineni
2019-12-17 16:46 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 09/15] ASoC: tegra: Add fallback for audio mclk Sowjanya Komatineni
2019-12-06 17:49 ` Sowjanya Komatineni
2019-12-06 17:56 ` Greg KH
2019-12-09 16:40 ` Mark Brown
2019-12-09 20:31 ` Dmitry Osipenko
2019-12-09 20:47 ` Mark Brown
2019-12-10 18:24 ` Dmitry Osipenko
2019-12-10 18:59 ` Mark Brown
2019-12-12 2:17 ` Dmitry Osipenko
2019-12-06 2:48 ` [PATCH v3 10/15] clk: tegra: Remove extern1 and cdev1 from clocks inittable Sowjanya Komatineni
2019-12-06 2:48 ` [PATCH v3 11/15] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni
2019-12-07 14:26 ` [PATCH v3 00/15] Move PMC clocks into Tegra PMC driver Dmitry Osipenko
2019-12-07 19:22 ` Sowjanya Komatineni
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