Re: [PATCH] perf/x86: KVM: Disable vPMU support on hybrid CPUs (host PMUs)

["Liang, Kan" <kan.liang@linux.intel.com>]

On 2023-01-20 12:32 p.m., Sean Christopherson wrote:
> On Fri, Jan 20, 2023, Liang, Kan wrote:
>>
>> On 2023-01-19 7:40 p.m., Sean Christopherson wrote:
>>> Disable KVM support for virtualizing PMUs on hosts with hybrid PMUs until
>>> KVM gains a sane way to enumeration the hybrid vPMU to userspace and/or
>>> gains a mechanism to let userspace opt-in to the dangers of exposing a
>>> hybrid vPMU to KVM guests.
>>>
>>> Virtualizing a hybrid PMU, or at least part of a hybrid PMU, is possible,
>>> but it requires userspace to pin vCPUs to pCPUs to prevent migrating a
>>> vCPU between a big core and a little core, requires the VMM to accurately
>>> enumerate the topology to the guest (if exposing a hybrid CPU to the
>>> guest), and also requires the VMM to accurately enumerate the vPMU
>>> capabilities to the guest.
>>
>> Current kernel only return the common counters to KVM, which is
>> available on both e-core and p-core. In theory, there should be no
>> problem with the migration between cores. You don't have to pin vCPU.
>> The only problem is that you probably can only use the architecture events.
> 
> And how exactly is KVM supposed to tell the guest that it can only use
> architectural events?  I see CPUID bits that enumerate which architectural events
> are supported, but I'm not seeing anything that says _only_ architectural events
> are supported.

I think we have to use a white list in KVM. For the unsupported event,
KVM will not create the event.

> 
>> There is nothing wrong for the information provided by the kernel. I
>> think it should be a KVM issue (my guess is the CPUID enumeration.) we
>> should fix rather than simply disable the PMU for entire hybrid machines.
> 
> I'm not arguing this isn't KVM's problem, and I'm all for proper enabling in KVM,
> but I'm not seeing any patches being posted.  In the meantime, we've got bug reports
> coming in about KVM guests having PMU problems on hybrid hosts, and a pile of
> evidence that strongly suggests this isn't going to be fixed by a one-line patch.
> 
> Again, I'm not against enabling vPMU on hybrid CPUs, but AFAICT the enabling is
> non-trivial and may require new uAPI to provide the necessary information to
> userspace.  As a short term fix, and something that can be backported to stable
> trees, I don't see a better alternative than disabling vPMU support.

I just did some tests with the latest kernel on a RPL machine, and
observed the below error in the guest.

[    0.118214] unchecked MSR access error: WRMSR to 0x38f (tried to
write 0x00011000f0000003f) at rIP: 0xffffffff83082124
(native_write_msr+0x4/0x30)
[    0.118949] Call Trace:
[    0.119092]  <TASK>
[    0.119215]  ? __intel_pmu_enable_all.constprop.0+0x88/0xe0
[    0.119533]  intel_pmu_enable_all+0x15/0x20
[    0.119778]  x86_pmu_enable+0x17c/0x320


The error is caused by the access to an unsupported bit (bit 48).
The bit is to enable the Perf Metrics feature, which is a p-core only
feature.

KVM doesn't support the feature, so the corresponding bit of
PERF_CAPABILITIES MSR is not exposed to the guest. For a non-hybrid
platform, guest checks the bit. Everything works well.

However, the current implementation in perf kernel for ADL and RPL
doesn't check the bit. Because the bit is not reliable on ADL and RPL.
Perf assumes that the p-core hardware always has the feature enabled.
There is no problem for the bare metal, but seems bring troubles on KVM.

There is no such issue for the later platforms anymore, e.g., MTL, since
we enhance the PMU features enumeration for the hybrid platforms.
Please find the enhancement in Chapter 10 NEXT GENERATION PERFORMANCE
MONITORING UNIT (PMU)
https://cdrdv2-public.intel.com/671368/architecture-instruction-set-extensions-programming-reference.pdf

I think, for a short term fix, we should fix the issue in the perf
kernel for ADL and RPL, rather than disable the entire vPMU on a hybrid
platform.

How about the below patch?


diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index dfd2c124cdf8..d667e8b79286 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6459,7 +6459,13 @@ __init int intel_pmu_init(void)
 					__EVENT_CONSTRAINT(0, (1ULL << pmu->num_counters) - 1,
 							   0, pmu->num_counters, 0, 0);
 		pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
-		pmu->intel_cap.perf_metrics = 1;
+		/*
+		 * The perf metrics bit is not reliable on ADL and RPL. For bare
+		 * metal, it's safe to assume that the feature is always enabled
+		 * on p-core, but we cannot do the same assumption for KVM.
+		 */
+		if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
+			pmu->intel_cap.perf_metrics = 1;
 		pmu->intel_cap.pebs_output_pt_available = 0;

 		memcpy(pmu->hw_cache_event_ids, spr_hw_cache_event_ids,
sizeof(pmu->hw_cache_event_ids));


Thanks,
Kan