From: Yakir Yang <ykk@rock-chips.com>
To: Sean Paul <seanpaul@chromium.org>
Cc: "Mark Yao" <yzq@rock-chips.com>,
"Inki Dae" <inki.dae@samsung.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
linux-rockchip@lists.infradead.org,
"Daniel Vetter" <daniel.vetter@ffwll.ch>,
"Emil Velikov" <emil.l.velikov@gmail.com>,
"Douglas Anderson" <dianders@chromium.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
"Javier Martinez Canillas" <javier@osg.samsung.com>,
"Tomasz Figa" <tomasz.figa@chromium.com>,
"Stéphane Marchesin" <marcheu@chromium.org>,
"Thierry Reding" <treding@nvidia.com>,
"Dan Carpenter" <dan.carpenter@oracle.com>
Subject: Re: [PATCH v3 04/10] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
Date: Wed, 29 Jun 2016 15:13:29 +0800 [thread overview]
Message-ID: <57737519.3040202@rock-chips.com> (raw)
In-Reply-To: <CAOw6vbKr68PMMNyptZas18Z0JPLyqnX+t+EvQSCy=i5tsbQKRA@mail.gmail.com>
Sean,
On 06/23/2016 09:27 PM, Sean Paul wrote:
> On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> As vendor document indicate, when REF_CLK bit set 0, then DP
>> phy's REF_CLK should switch to 24M source clock.
>>
>> But due to IC PHY layout mistaken, some chips need to flip this
>> bit(like RK3288), and unfortunately they didn't indicate in the
>> DP version register. That's why we have to make this little hack.
>>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
>> ---
>> Changes in v3:
>> - Make this hack code more clear (Tomasz, reviewed at Google Gerrit)
>> reg = ~reg & REF_CLK_MASK; ---> reg ^= REF_CLK_MASK;
>> [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c@80]
>> - Add tested flag from Javier
>>
>> Changes in v2:
>> - new patch in v2
>>
>> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 6 +++++-
>> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 +
>> drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 3 +++
>> include/drm/bridge/analogix_dp.h | 5 +++++
>> 4 files changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> index 931a76c..97ced6b 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>> @@ -75,7 +75,11 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
>> writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
>>
>> if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP)) {
>> - writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
>> + reg = REF_CLK_24M;
>> + if (dp->plat_data->subdev_type == RK3288_DP)
>> + reg ^= REF_CLK_MASK;
>> +
>> + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
>> writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
>> writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
>> writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> index 88d56ad..cdcc6c5 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>> @@ -165,6 +165,7 @@
>> /* ANALOGIX_DP_PLL_REG_1 */
>> #define REF_CLK_24M (0x1 << 0)
>> #define REF_CLK_27M (0x0 << 0)
>> +#define REF_CLK_MASK (0x1 << 0)
>>
>> /* ANALOGIX_DP_LANE_MAP */
>> #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
>> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> index 3855f46..315ebba 100644
>> --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>> @@ -46,6 +46,7 @@ struct rockchip_dp_chip_data {
>> u32 lcdsel_grf_reg;
>> u32 lcdsel_big;
>> u32 lcdsel_lit;
>> + u32 chip_type;
>> };
>>
>> struct rockchip_dp_device {
>> @@ -286,6 +287,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
>> dp->plat_data.encoder = &dp->encoder;
>>
>> dp->plat_data.dev_type = ROCKCHIP_DP;
>> + dp->plat_data.subdev_type = dp_data->chip_type;
>> dp->plat_data.power_on = rockchip_dp_poweron;
>> dp->plat_data.power_off = rockchip_dp_powerdown;
>>
>> @@ -384,6 +386,7 @@ static const struct rockchip_dp_chip_data rk3288_dp = {
>> .lcdsel_grf_reg = 0x025c,
>> .lcdsel_big = 0 | BIT(21),
>> .lcdsel_lit = BIT(5) | BIT(21),
>> + .chip_type = RK3288_DP,
>> };
>>
>> static const struct of_device_id rockchip_dp_dt_ids[] = {
>> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
>> index 9e5d013..06c0250 100644
>> --- a/include/drm/bridge/analogix_dp.h
>> +++ b/include/drm/bridge/analogix_dp.h
>> @@ -18,8 +18,13 @@ enum analogix_dp_devtype {
>> ROCKCHIP_DP,
>> };
>>
>> +enum analogix_dp_sub_devtype {
>> + RK3288_DP,
>> +};
>> +
>> struct analogix_dp_plat_data {
>> enum analogix_dp_devtype dev_type;
>> + enum analogix_dp_sub_devtype subdev_type;
>
> So this is what I was talking about in my review of the first patch of
> the series.
>
> I don't personally think the dev and subdev types add any clarity
> here, just more state. I'd prefer that you put the product number in
> the top level devtype, and add a helper function like:
>
> static bool is_rockchip(enum analogix_dp_devtype type) {
> return type == ... || type == ...
> }
Good idea, done.
Thanks,
- Yakir
> Sean
>
>> struct drm_panel *panel;
>> struct drm_encoder *encoder;
>> struct drm_connector *connector;
>> --
>> 1.9.1
>>
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
next prev parent reply other threads:[~2016-06-29 7:13 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 11:45 [PATCH v3 0/10] Yakir Yang
2016-06-14 11:46 ` [PATCH v3 01/10] drm/bridge: analogix_dp: rename RK3288_DP to ROCKCHIP_DP Yakir Yang
2016-06-23 13:20 ` Sean Paul
2016-06-14 11:46 ` [PATCH v3 02/10] drm/rockchip: analogix_dp: split the lcdc select setting into device data Yakir Yang
2016-06-23 14:32 ` Sean Paul
2016-06-23 16:16 ` Heiko Stuebner
2016-06-29 7:09 ` [PATCH v3 02/10] drm/rockchip: analogix_dp: split the lcdc select setting into device data[Involving remittance information, please pay attention to the safety of property] Yakir Yang
2016-06-14 11:46 ` [PATCH v3 03/10] drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 Yakir Yang
2016-06-23 14:33 ` Sean Paul
2016-06-29 7:11 ` Yakir Yang
2016-06-14 11:46 ` [PATCH v3 04/10] drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting Yakir Yang
2016-06-23 13:27 ` Sean Paul
2016-06-29 7:13 ` Yakir Yang [this message]
2016-06-14 11:46 ` [PATCH v3 05/10] drm/rockchip: analogix_dp: add rk3399 eDP support Yakir Yang
2016-06-14 15:24 ` Doug Anderson
2016-06-15 1:56 ` Yakir Yang
2016-06-23 13:48 ` Sean Paul
2016-06-29 6:58 ` Yakir Yang
2016-06-14 11:46 ` [PATCH v3 06/10] drm/rockchip: analogix_dp: make panel detect to an optional action Yakir Yang
2016-06-23 14:10 ` Sean Paul
2016-06-29 6:43 ` Yakir Yang
2016-06-14 11:46 ` [PATCH v3 07/10] drm/bridge: analogix_dp: passing the connector as an argument in .get_modes() Yakir Yang
2016-06-14 16:26 ` Daniel Vetter
2016-06-14 16:26 ` Daniel Vetter
2016-06-14 16:28 ` Daniel Vetter
2016-06-15 1:58 ` Yakir Yang
2016-06-23 14:11 ` Sean Paul
2016-06-14 11:46 ` [PATCH v3 08/10] drm/rockchip: analogix_dp: correct the connector display color format and bpc Yakir Yang
2016-06-23 14:19 ` Sean Paul
2016-06-29 6:41 ` Yakir Yang
2016-06-14 11:46 ` [PATCH v3 09/10] drm/rockchip: analogix_dp: update the comments about why need to hardcode VOP output mode Yakir Yang
2016-06-23 14:22 ` Sean Paul
2016-06-29 6:42 ` Yakir Yang
2016-06-14 11:46 ` [PATCH v3 10/10] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in Yakir Yang
2016-06-22 2:31 ` [PATCH v3.1 1/2] drm/rockchip: analogix_dp: introduce the pclk for grf Yakir Yang
2016-06-23 1:46 ` [PATCH v4 " Yakir Yang
2016-06-23 1:47 ` [PATCH v4 2/2] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name Yakir Yang
2016-06-23 5:17 ` Doug Anderson
2016-06-29 3:32 ` Yakir Yang
2016-06-23 1:58 ` [PATCH v4.1 1/2] drm/rockchip: analogix_dp: introduce the pclk for grf Yakir Yang
2016-06-23 5:16 ` Doug Anderson
2016-06-29 3:35 ` Yakir Yang
2016-06-22 2:31 ` [PATCH v3.1 2/2] dt-bindings: analogix_dp: rockchip: correct the wrong compatible name Yakir Yang
2016-06-23 14:24 ` [PATCH v3 10/10] drm/bridge: analogix_dp: fix no drm hpd event when panel plug in Sean Paul
2016-06-29 3:35 ` Yakir Yang
2016-06-21 13:46 ` [PATCH v3 0/10] Archit Taneja
2016-06-22 2:24 ` Yakir Yang
2016-06-22 3:23 ` Archit Taneja
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