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([2001:b07:6468:f312:e044:3d2:1991:920c]) by smtp.gmail.com with ESMTPSA id d4sm19487104wre.22.2020.06.01.02.21.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jun 2020 02:21:42 -0700 (PDT) Subject: Re: [PATCH RFCv2 9/9] arm64: Support async page fault To: Marc Zyngier Cc: Gavin Shan , kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org, shan.gavin@gmail.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org References: <20200508032919.52147-1-gshan@redhat.com> <20200508032919.52147-10-gshan@redhat.com> <81adf013-3de7-23e6-7648-8aec821b033c@redhat.com> <8ab64c6a-582b-691d-79ab-21cdc0455cd3@redhat.com> <6a4a82a4-af01-98c2-c854-9199f55f7bd3@redhat.com> <6965aaf641a23fab64fbe2ceeb790272@kernel.org> <4337cca152df47c93d96e092189a0e36@kernel.org> From: Paolo Bonzini Message-ID: <5c72c597-732e-7dbf-d056-665674ec1792@redhat.com> Date: Mon, 1 Jun 2020 11:21:41 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <4337cca152df47c93d96e092189a0e36@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/05/20 14:44, Marc Zyngier wrote: >> >> Is there an ARM-approved way to reuse the S2 fault syndromes to detect >> async page faults? > > It would mean being able to set an ESR_EL2 register value into ESR_EL1, > and there is nothing in the architecture that would allow that, I understand that this is not what you want to do and I'm not proposing it, but I want to understand this better: _in practice_ do CPUs check closely what is written in ESR_EL1? In any case, the only way to implement this, it seems to me, would be a completely paravirtualized exception vector that doesn't use ESR at all. On the other hand, for the page ready (interrupt) side assigning a PPI seems complicated but doable. Paolo > with > the exception of nested virt: a VHE guest hypervisor running at EL1 > must be able to observe S2 faults for its own S2, as synthesized by > the host hypervisor. > The trouble is that: > - there is so far no commercially available CPU supporting NV > - even if you could get hold of such a machine, there is no >   guarantee that such "EL2 syndrome at EL1" is valid outside of >   the nested context > - this doesn't solve the issue for non-NV CPUs anyway