From: Dan Williams <dan.j.williams@intel.com>
To: "Jonathan Zhang (Infra)" <jonzhang@fb.com>,
Dan Williams <dan.j.williams@intel.com>
Cc: Robert Richter <rrichter@amd.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Ira Weiny" <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>
Subject: Re: [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode)
Date: Thu, 8 Sep 2022 14:02:07 -0700 [thread overview]
Message-ID: <631a584f46cc9_166f2946@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <14D1BEC2-4921-46AD-B767-3A7E555F6E97@fb.com>
Jonathan Zhang (Infra) wrote:
>
>
> > On Sep 8, 2022, at 12:51 PM, Dan Williams <dan.j.williams@intel.com> wrote:
> >
> > !-------------------------------------------------------------------|
> > This Message Is From an External Sender
> >
> > |-------------------------------------------------------------------!
> >
> > Jonathan Zhang (Infra) wrote:
> >>
> >>
> >>> On Sep 7, 2022, at 10:43 PM, Dan Williams <dan.j.williams@intel.com> wrote:
> >>>
> >>> Apologies for the delay in getting to this I had hoped to be able to
> >>> finish up some other DAX work to focus on this, but time is getting
> >>> short so I will need to do both in parallel.
> >>>
> >>> Robert Richter wrote:
> >>>> In Restricted CXL Device (RCD) mode (formerly referred to as CXL 1.1)
> >>>> the PCIe enumeration hierarchy is different from CXL VH Enumeration
> >>>> (formerly referred to as 2.0, for both modes see CXL spec 3.0: 9.11
> >>>> and 9.12, [1]). This series adds support for RCD mode. It implements
> >>>> the detection of Restricted CXL Hosts (RCHs) and its corresponding
> >>>> Restricted CXL Devices (RCDs). It does the necessary enumeration of
> >>>> ports and connects the endpoints. With all the plumbing an RCH/RCD
> >>>> pair is registered at the Linux CXL bus and becomes visible in sysfs
> >>>> in the same way as CXL VH hosts and devices do already. RCDs are
> >>>> brought up as CXL endpoints and bound to subsequent drivers such as
> >>>> cxl_mem.
> >>>>
> >>>> For CXL VH the host driver (cxl_acpi) starts host bridge discovery
> >>>> once the ACPI0017 CXL root device is detected and then searches for
> >>>> ACPI0016 host bridges to enable CXL. In RCD mode an ACPI0017 device
> >>>> might not necessarily exist
> >>>
> >>> That's a broken BIOS as far as I can see. No ACPI0017 == no OS CXL
> >>> services and the CXL aspects of the device need to be 100% managed by
> >>> the BIOS. You can still run the cxl_pci driver in that case for mailbox
> >>> operation, but error handling must be firmware-first without ACPI0017.
> >> Firmware-first or OS-first applies to CXL protocol error handling. For CXL
> >> memory error handling, the device generates a DRAM error record, the OS
> >> parses such record and act accordingly. According to CXL spec (section
> >> 8.2.9.2.1.2 DRAM Event Record), DPA but not HPA is in such record. The OS
> >> needs to translate such DPA into HPA to act on. I am taking this as an example
> >> to show that OS CXL services is needed.
> >> Instead of using ACPI0016 to tell whether the system is under RCH mode,
> >> I suppose one way is to check “CXL version” field of CHBS structure in CEDT?
> >
> > Unless the OS has negotiated CXL _OSC the BIOS owns the event retrieval
> > and translating it from DPA to HPA. I do want to add OS CXL services to
> > Linux, but only in the case when the BIOS is actively enabling OS native
> > address translation which includes populating ACPI0017, CFMWS, and
> > devices with the HDM decoder capability registers instead of DVSEC range
> > registers. Everything else is early-gen CXL that is 100% BIOS supported,
> > similar to DDR where a driver is not expected.
>
>
> It makes sense that the BIOS and OS need to negotiate CXL _OSC so that OS
> would take care of address translation. That being said, only DVSEC range
> register (but not HDM decoder capability register) is available when the device is in
> RCRB mode (section 9.11.8 figure 9-7) attached to a RCH. This type of
> configuration needs to be supported with OS CXL service.
>
So that figure does have the HDM capabilty pictured in the RCD upstream
port. However, Table 8-22 does seem to incidate that Type 3 D1 devices
are not permitted to have an HDM Decoder Capabilitiy Structure.
However that then leave me confused about figure 9-8 as that shows an
HDM decoder capability in the BAR and not the RCRB. Is that picture
wrong with respect what Table 8-22 indicates?
next prev parent reply other threads:[~2022-09-08 21:02 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 8:15 [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-08-31 8:15 ` [PATCH 01/15] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-08-31 8:54 ` Jonathan Cameron
2022-09-01 5:21 ` Robert Richter
2022-08-31 9:39 ` kernel test robot
2022-09-07 16:11 ` [PATCH 1/15] " Davidlohr Bueso
2022-09-09 10:38 ` Robert Richter
2022-09-08 5:44 ` [PATCH 01/15] " Dan Williams
2022-09-08 14:51 ` Robert Richter
2022-09-08 19:47 ` Dan Williams
2022-08-31 8:15 ` [PATCH 02/15] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-08-31 8:56 ` Jonathan Cameron
2022-09-01 5:31 ` Robert Richter
2022-09-08 5:48 ` Dan Williams
2022-09-09 12:19 ` Robert Richter
2022-09-16 18:04 ` Dan Williams
2022-09-28 10:28 ` Robert Richter
2022-09-30 19:07 ` Dan Williams
2022-08-31 8:15 ` [PATCH 03/15] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-08-31 9:59 ` Jonathan Cameron
2022-09-01 5:36 ` Robert Richter
2022-09-06 7:30 ` Robert Richter
2022-09-06 8:52 ` Jonathan Cameron
2022-09-07 16:21 ` [PATCH 3/15] " Davidlohr Bueso
2022-09-08 5:53 ` [PATCH 03/15] " Dan Williams
2022-09-28 10:32 ` Robert Richter
2022-08-31 8:15 ` [PATCH 04/15] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-09-07 16:29 ` [PATCH 4/15] " Davidlohr Bueso
2022-09-08 5:55 ` [PATCH 04/15] " Dan Williams
2022-08-31 8:15 ` [PATCH 05/15] cxl/acpi: Add probe function to detect restricted CXL hosts in RCD mode Robert Richter
2022-08-31 10:08 ` Jonathan Cameron
2022-09-01 6:01 ` Robert Richter
2022-09-01 10:10 ` Jonathan Cameron
2022-09-06 7:19 ` Robert Richter
2022-09-06 8:53 ` Jonathan Cameron
2022-09-07 18:22 ` Bjorn Helgaas
2022-09-08 6:00 ` Dan Williams
2022-09-08 6:11 ` Dan Williams
2022-08-31 8:15 ` [PATCH 06/15] PCI/ACPI: Link host bridge to its ACPI fw node Robert Richter
2022-08-31 10:11 ` Jonathan Cameron
2022-09-07 18:37 ` Bjorn Helgaas
2022-09-07 20:15 ` Rafael J. Wysocki
2022-09-08 6:05 ` Dan Williams
2022-09-08 13:06 ` Rafael J. Wysocki
2022-09-08 19:45 ` Dan Williams
2022-09-09 10:20 ` Robert Richter
2022-09-14 22:11 ` Bjorn Helgaas
2022-09-16 23:16 ` Dan Williams
2022-09-08 13:04 ` Rafael J. Wysocki
2022-08-31 8:15 ` [PATCH 07/15] cxl/acpi: Check RCH's PCIe Host Bridge ACPI ID Robert Richter
2022-08-31 10:20 ` Jonathan Cameron
2022-09-01 6:16 ` Robert Richter
2022-09-01 10:14 ` Jonathan Cameron
2022-09-08 6:11 ` Dan Williams
2022-08-31 8:15 ` [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities Robert Richter
2022-08-31 10:52 ` Jonathan Cameron
2022-08-31 11:12 ` Jonathan Cameron
2022-09-01 6:38 ` Robert Richter
2022-09-01 10:37 ` Jonathan Cameron
2022-09-06 10:20 ` Robert Richter
2022-09-01 6:30 ` Robert Richter
2022-09-01 10:23 ` Jonathan Cameron
2022-09-08 6:18 ` Dan Williams
2022-08-31 8:15 ` [PATCH 09/15] cxl/acpi: Determine PCI host bridge's ACPI UID Robert Richter
2022-08-31 11:00 ` Jonathan Cameron
2022-09-01 6:53 ` Robert Richter
2022-09-01 10:41 ` Jonathan Cameron
2022-09-08 6:18 ` Dan Williams
2022-09-08 20:47 ` Jonathan Zhang (Infra)
2022-09-08 21:10 ` Dan Williams
2022-09-08 21:35 ` Jonathan Zhang (Infra)
2022-09-08 22:31 ` Dan Williams
2022-09-08 22:41 ` Jonathan Zhang (Infra)
2022-08-31 8:15 ` [PATCH 10/15] cxl/acpi: Extract the RCH's RCRB base address from CEDT Robert Richter
2022-08-31 11:09 ` Jonathan Cameron
2022-09-01 7:04 ` Robert Richter
2022-08-31 8:15 ` [PATCH 11/15] cxl/acpi: Extract the host's component register base address from RCRB Robert Richter
2022-08-31 11:56 ` Jonathan Cameron
2022-09-01 7:38 ` Robert Richter
2022-09-01 11:00 ` Jonathan Cameron
2022-09-06 11:32 ` Robert Richter
2022-09-08 20:59 ` Jonathan Zhang (Infra)
2022-08-31 8:16 ` [PATCH 12/15] cxl/acpi: Skip devm_cxl_port_enumerate_dports() when in RCD mode Robert Richter
2022-08-31 11:58 ` Jonathan Cameron
2022-09-01 7:40 ` Robert Richter
2022-08-31 8:16 ` [PATCH 13/15] cxl/acpi: Rework devm_cxl_enumerate_ports() to support " Robert Richter
2022-08-31 12:11 ` Jonathan Cameron
2022-09-01 7:50 ` Robert Richter
2022-08-31 8:16 ` [PATCH 14/15] cxl/acpi: Enumerate ports in RCD mode to enable RCHs and RCDs Robert Richter
2022-08-31 12:16 ` Jonathan Cameron
2022-09-01 7:54 ` Robert Richter
2022-08-31 8:16 ` [PATCH 15/15] cxl/acpi: Specify module load order dependency for the cxl_acpi module Robert Richter
2022-09-16 18:12 ` Dan Williams
2022-08-31 12:23 ` [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Jonathan Cameron
2022-09-01 8:19 ` Robert Richter
2022-09-08 6:41 ` Dan Williams
2022-09-08 5:43 ` Dan Williams
2022-09-08 18:52 ` Jonathan Zhang (Infra)
2022-09-08 19:51 ` Dan Williams
2022-09-08 20:36 ` Jonathan Zhang (Infra)
2022-09-08 21:02 ` Dan Williams [this message]
2022-09-16 18:16 ` Dan Williams
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