From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06972C47096 for ; Tue, 1 Jun 2021 12:51:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFAF461028 for ; Tue, 1 Jun 2021 12:51:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233823AbhFAMxU (ORCPT ); Tue, 1 Jun 2021 08:53:20 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:22124 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232965AbhFAMxS (ORCPT ); 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Tue, 01 Jun 2021 14:51:23 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B97210002A; Tue, 1 Jun 2021 14:51:22 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 127BA221775; Tue, 1 Jun 2021 14:51:22 +0200 (CEST) Received: from lmecxl0573.lme.st.com (10.75.127.46) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 1 Jun 2021 14:51:20 +0200 Subject: Re: [PATCH 4/4] clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after kernel startup To: , , , , , , , CC: , , , , , , , , References: <1620990152-19255-1-git-send-email-dillon.minfei@gmail.com> <1620990152-19255-5-git-send-email-dillon.minfei@gmail.com> From: Patrice CHOTARD Message-ID: <6915fa2a-e211-476f-8317-6825e280c322@foss.st.com> Date: Tue, 1 Jun 2021 14:51:20 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1620990152-19255-5-git-send-email-dillon.minfei@gmail.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-06-01_06:2021-05-31,2021-06-01 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Dillon On 5/14/21 1:02 PM, dillon.minfei@gmail.com wrote: > From: Dillon Min > > stm32's clk driver register two ltdc gate clk to clk core by > clk_hw_register_gate() and clk_hw_register_composite() > > first: 'stm32f429_gates[]', clk name is 'ltdc', which no user to use. > second: 'stm32f429_aux_clk[]', clk name is 'lcd-tft', used by ltdc driver > > both of them point to the same offset of stm32's RCC register. after > kernel enter console, clk core turn off ltdc's clk as 'stm32f429_gates[]' > is no one to use. but, actually 'stm32f429_aux_clk[]' is in use. > > Fixes: daf2d117cbca ("clk: stm32f4: Add lcd-tft clock") > Signed-off-by: Dillon Min > Acked-by: Stephen Boyd > Link: https://lore.kernel.org/linux-arm-kernel/1590564453-24499-7-git-send-email-dillon.minfei@gmail.com/ > --- > drivers/clk/clk-stm32f4.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c > index 42ca2dd86aea..f4156a8a6041 100644 > --- a/drivers/clk/clk-stm32f4.c > +++ b/drivers/clk/clk-stm32f4.c > @@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { > { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, > - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, > }; > > static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { > @@ -211,7 +210,6 @@ static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { > { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, > - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, > }; > > static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { > @@ -286,7 +284,6 @@ static const struct stm32f4_gate_data stm32f746_gates[] __initconst = { > { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, > - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, > }; > > static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { > @@ -364,7 +361,6 @@ static const struct stm32f4_gate_data stm32f769_gates[] __initconst = { > { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" }, > - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, > { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" }, > }; > > Reviewed-by: Patrice Chotard Thanks Patrice