From: Randy Dunlap <rdunlap@infradead.org>
To: Ramakrishna Saripalli <rsaripal@amd.com>,
linux-kernel@vger.kernel.org, x86@kernel.org, tglx@linutronix.de,
mingo@redhat.com, bp@alien8.de, Jonathan Corbet <corbet@lwn.net>
Subject: Re: [PATCH 5/5] x86/speculation: Add PSF mitigation kernel parameters
Date: Thu, 8 Apr 2021 20:43:07 -0700 [thread overview]
Message-ID: <72b45d78-f66b-bd18-4931-04feb206cd79@infradead.org> (raw)
In-Reply-To: <20210407125024.242491-1-rsaripal@amd.com>
On 4/7/21 5:50 AM, Ramakrishna Saripalli wrote:
> From: Ramakrishna Saripalli <rk.saripalli@amd.com>
>
> PSF mitigation introduces new kernel parameters.
>
> The kernel parameters for PSF mitigation are modeled
> after spec_store_bypass_disable.
Maybe too much copy-pasta. See below.
>
> Signed-off-by: Ramakrishna Saripalli<rk.saripalli@amd.com>
> ---
> .../admin-guide/kernel-parameters.txt | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 04545725f187..68dfde77a87d 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -2876,6 +2876,7 @@
> nospectre_v2 [X86,PPC,S390,ARM64]
> spectre_v2_user=off [X86]
> spec_store_bypass_disable=off [X86,PPC]
> + psfd=off [X86]
> ssbd=force-off [ARM64]
> l1tf=off [X86]
> mds=off [X86]
> @@ -3243,6 +3244,8 @@
>
> nohugeiomap [KNL,X86,PPC,ARM64] Disable kernel huge I/O mappings.
>
> + nopsfd [HW,X86] Disable mitigation for Predictive Store Forwarding.
> +
> nosmt [KNL,S390] Disable symmetric multithreading (SMT).
> Equivalent to smt=1.
>
> @@ -4002,6 +4005,48 @@
> that).
> Format: <bool>
>
> + psfd= [HW,X86]
> + Predictive Store Forwarding Disable control
> +
> + Certain AMD processors feature a new technology called Predictive
> + Store Forwarding. This feature is designed to improve the
> + performance of code execution by predicting dependencies
> + between loads and stores.
> +
> + Modern processors implement techniques to optimize the
> + execution of a load instruction to an address that was
> + recently written by a store instruction.
> +
> + PSF expands on the above by speculating on the relationship
> + between loads and stores without waiting for address
> + calculation to complete. With PSF, CPU learns over time the
> + relationship between loads and stores.
> +
> + Incorrect PSF predictions can occur for various reasons.
> + Please see the AMD PSF whitepaper for more information.
> +
> + All AMD processors that implement PSF also provide ability
> + to control mitigation of PSF.
> +
> + Following options are provided to control PSF mitigation.
> +
> + The options are:
> + on - Unconditionally disable Speculative Store Bypass
PSF.
> + off - Unconditionally enable Speculative Store Bypass
PSF.
> + auto - Kernel detects whether the CPU is vulnerable.
> + If the CPU is not vulnerable, off is selected.
> + If the CPU is vulnerable, default mitigation is
> + KConfig dependent.
> + prctl - Control Predictive Store Forwarding per thread
> + via prctl. Predictive Store Forwarding is enabled
> + per process by default. The state of the control
> + is inherited on fork.
> + seccomp - Same as prctl above but all seccomp threads will
> + disable PSF unless they opt out.
> +
> + Default mitigations:
> + [X86] If CONFIG_SECCOMP=y "seccomp" else "prctl"
> +
> psi= [KNL] Enable or disable pressure stall information
> tracking.
> Format: <bool>
>
--
~Randy
next prev parent reply other threads:[~2021-04-09 3:43 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 12:50 [PATCH 5/5] x86/speculation: Add PSF mitigation kernel parameters Ramakrishna Saripalli
2021-04-09 3:43 ` Randy Dunlap [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-04-06 15:49 [PATCH 0/5] Introduce support for PSF mitigation Ramakrishna Saripalli
2021-04-06 15:50 ` [PATCH 5/5] x86/speculation: Add PSF mitigation kernel parameters Ramakrishna Saripalli
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