Re: [PATCH] clk: mmp2: avoid disabling the SP clock when unused

[Lubomir Rintel <lkundrak@v3.sk>]

On Wed, 2019-01-16 at 08:37 -0800, Stephen Boyd wrote:
> Quoting Lubomir Rintel (2019-01-16 01:35:05)
> > There could be vital functionality running on the SP PJ1 core it can not be
> > restarted just by turning the clock back on.
> > 
> > On the OLPC laptop, the keyboard controller code runs there. It
> > wouldn't be possible to load the driver for it as a module if the clock
> > is disabled on boot.
> > 
> > Cc: stable@vger.kernel.org # v4.18+
> > Fixes: commit fc27c2394d96 ("clk: mmp2: add SP clock")
> > Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> > ---
> >  drivers/clk/mmp/clk-of-mmp2.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
> > index f2a1c9bbaa63..3e33f1295f59 100644
> > --- a/drivers/clk/mmp/clk-of-mmp2.c
> > +++ b/drivers/clk/mmp/clk-of-mmp2.c
> > @@ -246,7 +246,7 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = {
> >         {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
> >         {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
> >         {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
> > -       {MMP2_CLK_SP, "sp_clk", NULL, CLK_SET_RATE_PARENT, APMU_SP, 0x1b, 0x1b, 0x0, 0, &sp_lock},
> > +       {MMP2_CLK_SP, "sp_clk", NULL, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, APMU_SP, 0x1b, 0x1b, 0x0, 0, &sp_lock},
> 
> Is it a critical clk that should never be turned off?

I don't think it is. It is entirely plausible to have no use for the
"security processor", and in that case it's just okay to keep the clock
disabled.

> If so, mark it as
> CLK_IS_CRITICAL. Either way, please add a comment in the code about why
> CLK_IGNORE_UNUSED or CLK_IS_CRITICAL is used.

Okay.

Thanks,
Lubo