From: Marek Vasut <marek.vasut@gmail.com>
To: Cyrille Pitchen <cyrille.pitchen@atmel.com>,
linux-mtd@lists.infradead.org
Cc: computersforpeace@gmail.com, dwmw2@infradead.org,
boris.brezillon@free-electrons.com, richard@nod.at,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 3/4] mtd: spi-nor: introduce Double Transfer Rate (DTR) SPI protocols
Date: Wed, 19 Apr 2017 01:05:58 +0200 [thread overview]
Message-ID: <73d701a3-cd56-70b2-cf15-ec16e6734481@gmail.com> (raw)
In-Reply-To: <be585167c61f5c057041b2079d477e0106e9be64.1492554665.git.cyrille.pitchen@atmel.com>
On 04/19/2017 12:51 AM, Cyrille Pitchen wrote:
> This patch introduces support to Double Transfer Rate (DTR) SPI protocols.
> DTR is used only for Fast Read operations.
>
> According to manufacturer datasheets, whatever the number of I/O lines
> used during instruction (x) and address/mode/dummy (y) clock cycles, DTR
> is used only during data (z) clock cycles of SPI x-y-z protocols.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[...]
> @@ -282,19 +305,22 @@ struct spi_nor_hwcaps {
> * As a matter of performances, it is relevant to use Quad SPI protocols first,
> * then Dual SPI protocols before Fast Read and lastly (Slow) Read.
> */
> -#define SNOR_HWCAPS_READ_MASK GENMASK(7, 0)
> +#define SNOR_HWCAPS_READ_MASK GENMASK(10, 0)
> #define SNOR_HWCAPS_READ BIT(0)
> #define SNOR_HWCAPS_READ_FAST BIT(1)
> -
> -#define SNOR_HWCAPS_READ_DUAL GENMASK(4, 2)
> -#define SNOR_HWCAPS_READ_1_1_2 BIT(2)
> -#define SNOR_HWCAPS_READ_1_2_2 BIT(3)
> -#define SNOR_HWCAPS_READ_2_2_2 BIT(4)
> -
> -#define SNOR_HWCAPS_READ_QUAD GENMASK(7, 5)
> -#define SNOR_HWCAPS_READ_1_1_4 BIT(5)
> -#define SNOR_HWCAPS_READ_1_4_4 BIT(6)
> -#define SNOR_HWCAPS_READ_4_4_4 BIT(7)
> +#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
> +
> +#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
> +#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
> +#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
> +#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
> +#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
> +
> +#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
> +#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
> +#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
> +#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
> +#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
I can't say I'm a big fan on this re-numeration when you add a new
entry. But unless you have a better idea, we'll have to live with this ...
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2017-04-18 23:07 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-18 22:51 [PATCH v7 0/4] mtd: spi-nor: parse SFDP tables to setup (Q)SPI memories Cyrille Pitchen
2017-04-18 22:51 ` [PATCH v7 1/4] mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols Cyrille Pitchen
2017-04-18 23:02 ` Marek Vasut
2017-04-19 20:12 ` Cyrille Pitchen
2017-04-19 20:49 ` Cyrille Pitchen
2017-04-19 21:31 ` Marek Vasut
2017-04-19 23:17 ` Cyrille Pitchen
2017-04-20 1:56 ` Marek Vasut
2017-04-18 22:51 ` [PATCH v7 2/4] mtd: m25p80: add support of SPI 1-2-2 and " Cyrille Pitchen
2017-04-18 22:51 ` [PATCH v7 3/4] mtd: spi-nor: introduce Double Transfer Rate (DTR) SPI protocols Cyrille Pitchen
2017-04-18 23:05 ` Marek Vasut [this message]
2017-04-19 20:20 ` Cyrille Pitchen
2017-04-19 21:35 ` Marek Vasut
2017-04-18 22:51 ` [PATCH v7 4/4] mtd: spi-nor: introduce Octo " Cyrille Pitchen
2017-04-18 23:06 ` Marek Vasut
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