From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PULL] memory: tegra: Changes for v5.14-rc1
Date: Thu, 3 Jun 2021 22:56:29 +0300 [thread overview]
Message-ID: <772bf62a-fb09-cec4-ed4d-ddbfc2832e2b@gmail.com> (raw)
In-Reply-To: <20210603143739.787957-1-thierry.reding@gmail.com>
03.06.2021 17:37, Thierry Reding пишет:
> memory: tegra: Changes for v5.14-rc1
>
> This stable tag contains Dmitry's power domain work, including all the
> necessary dependencies from the regulator, clock and ARM SoC trees.
>
> ----------------------------------------------------------------
> Dmitry Osipenko (18):
> clk: tegra30: Use 300MHz for video decoder by default
> clk: tegra: Fix refcounting of gate clocks
> clk: tegra: Ensure that PLLU configuration is applied properly
> clk: tegra: Halve SCLK rate on Tegra20
> clk: tegra: Don't allow zero clock rate for PLLs
> clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
> clk: tegra: Mark external clocks as not having reset control
> clk: tegra: Don't deassert reset on enabling clocks
> regulator: core: Add regulator_sync_voltage_rdev()
> soc/tegra: regulators: Bump voltages on system reboot
This patch is a build dependency prerequisite for the "soc/tegra:
regulators: Support core domain state syncing" patch. Will you send a
new PR to Krzysztof with the remaining soc/tegra patches?
next prev parent reply other threads:[~2021-06-03 19:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-03 14:37 [PULL] memory: tegra: Changes for v5.14-rc1 Thierry Reding
2021-06-03 19:45 ` Krzysztof Kozlowski
2021-06-03 19:56 ` Dmitry Osipenko [this message]
2021-06-04 9:32 ` Thierry Reding
2021-06-04 12:51 ` Dmitry Osipenko
2021-06-07 8:28 ` Krzysztof Kozlowski
2021-06-07 13:26 ` Thierry Reding
2021-06-07 13:41 ` Dmitry Osipenko
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