From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
Alex Williamson <alex.williamson@redhat.com>,
"Raj, Ashok" <ashok.raj@intel.com>,
Ingo Molnar <mingo@kernel.org>,
"David S. Miller" <davem@davemloft.net>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, Kevin Tian <kevin.tian@intel.com>,
x86@kernel.org
Subject: Re: [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP
Date: Thu, 22 Jul 2021 16:12:19 +0100 [thread overview]
Message-ID: <871r7q2xik.wl-maz@kernel.org> (raw)
In-Reply-To: <20210721192650.687529735@linutronix.de>
On Wed, 21 Jul 2021 20:11:32 +0100,
Thomas Gleixner <tglx@linutronix.de> wrote:
>
> X86 IO/APIC and MSI interrupts (when used without interrupts remapping)
> require that the affinity setup on startup is done before the interrupt is
> enabled for the first time as the non-remapped operation mode cannot safely
> migrate enabled interrupts from arbitrary contexts. Provide a new irq chip
> flag which allows affected hardware to request this.
>
> This has to be opt-in because there have been reports in the past that some
> interrupt chips cannot handle affinity setting before startup.
>
> Fixes: 18404756765c ("genirq: Expose default irq affinity mask (take 3)")
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Ingo Molnar <mingo@kernel.org>
> ---
> include/linux/irq.h | 2 ++
> kernel/irq/chip.c | 5 ++++-
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> --- a/include/linux/irq.h
> +++ b/include/linux/irq.h
> @@ -569,6 +569,7 @@ struct irq_chip {
> * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips
> * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs
> * in the suspend path if they are in disabled state
> + * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
> */
> enum {
> IRQCHIP_SET_TYPE_MASKED = (1 << 0),
> @@ -581,6 +582,7 @@ enum {
> IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
> IRQCHIP_SUPPORTS_NMI = (1 << 8),
> IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9),
> + IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
> };
>
> #include <linux/irqdesc.h>
> --- a/kernel/irq/chip.c
> +++ b/kernel/irq/chip.c
> @@ -265,8 +265,11 @@ int irq_startup(struct irq_desc *desc, b
> } else {
> switch (__irq_startup_managed(desc, aff, force)) {
> case IRQ_STARTUP_NORMAL:
> + if (d->chip->flags & IRQCHIP_AFFINITY_PRE_STARTUP)
> + irq_setup_affinity(desc);
How about moving this to activate instead? We already special-case the
activation of MSIs for PCI (MSI_FLAG_ACTIVATE_EARLY), and this
wouldn't look completely out of place. The startup mode could be an
issue though...
> ret = __irq_startup(desc);
> - irq_setup_affinity(desc);
> + if (!(d->chip->flags & IRQCHIP_AFFINITY_PRE_STARTUP))
> + irq_setup_affinity(desc);
> break;
> case IRQ_STARTUP_MANAGED:
> irq_do_set_affinity(d, aff, false);
Otherwise, looks good.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-07-22 15:12 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-21 19:11 [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Thomas Gleixner
2021-07-21 19:11 ` [patch 1/8] PCI/MSI: Enable and mask MSIX early Thomas Gleixner
2021-07-21 21:38 ` Raj, Ashok
2021-07-21 22:51 ` Thomas Gleixner
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:33 ` Thomas Gleixner
2021-07-21 19:11 ` [patch 2/8] PCI/MSI: Mask all unused MSI-X entries Thomas Gleixner
2021-07-21 22:23 ` Raj, Ashok
2021-07-21 22:57 ` Thomas Gleixner
2021-07-22 13:46 ` Marc Zyngier
2021-07-28 10:04 ` Thomas Gleixner
2021-07-22 21:45 ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 3/8] PCI/MSI: Enforce that MSI-X table entry is masked for update Thomas Gleixner
2021-07-21 22:32 ` Raj, Ashok
2021-07-21 22:59 ` Thomas Gleixner
2021-07-22 21:46 ` Bjorn Helgaas
2021-07-21 19:11 ` [patch 4/8] PCI/MSI: Enforce MSI[X] entry updates to be visible Thomas Gleixner
2021-07-22 21:48 ` Bjorn Helgaas
[not found] ` <CAHp75VdNi4rMuRz8UrW9Haf_Ge8KmNJ0w9ykheqkVhmpXHTUyg@mail.gmail.com>
2021-07-23 8:14 ` Marc Zyngier
2021-07-21 19:11 ` [patch 5/8] PCI/MSI: Simplify msi_verify_entries() Thomas Gleixner
2021-07-21 19:11 ` [patch 6/8] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP Thomas Gleixner
2021-07-22 15:12 ` Marc Zyngier [this message]
2021-07-28 10:40 ` Thomas Gleixner
2021-07-21 19:11 ` [patch 7/8] x86/ioapic: Force affinity setup before startup Thomas Gleixner
2021-07-21 19:11 ` [patch 8/8] x86/msi: " Thomas Gleixner
2021-07-21 21:10 ` [patch 0/8] PCI/MSI, x86: Cure a couple of inconsistencies Raj, Ashok
2021-07-21 22:39 ` Thomas Gleixner
2021-07-22 15:17 ` Marc Zyngier
2021-07-22 21:43 ` Bjorn Helgaas
2021-07-27 20:38 ` Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=871r7q2xik.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=alex.williamson@redhat.com \
--cc=ashok.raj@intel.com \
--cc=bhelgaas@google.com \
--cc=davem@davemloft.net \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).