From: Michael Ellerman <mpe@ellerman.id.au>
To: Stephane Eranian <eranian@google.com>
Cc: Madhavan Srinivasan <maddy@linux.ibm.com>,
Peter Zijlstra <peterz@infradead.org>,
linux-kernel@vger.kernel.org, acme@redhat.com, jolsa@redhat.com,
kim.phillips@amd.com, namhyung@kernel.org, irogers@google.com,
atrajeev@linux.vnet.ibm.com,
Arnaldo Carvalho de Melo <acme@kernel.org>
Subject: Re: [PATCH v1 01/13] perf/core: add union to struct perf_branch_entry
Date: Fri, 17 Sep 2021 22:38:37 +1000 [thread overview]
Message-ID: <874kajjs1e.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <CABPqkBRrx5vnPqTEnuQOeoJxyjiszCG7EMdK35ES=rHKYUNBpQ@mail.gmail.com>
Stephane Eranian <eranian@google.com> writes:
> Hi,
>
> On Fri, Sep 17, 2021 at 12:05 AM Michael Ellerman <mpe@ellerman.id.au> wrote:
>>
>> Stephane Eranian <eranian@google.com> writes:
>> > Hi,
>> >
>> > Thanks for fixing this in the perf tool. But what about the struct
>> > branch_entry in the header?
>>
>> I'm not sure what you mean.
>>
>> We can't change the order of the fields in the header, without breaking
>> existing userspace on BE systems.
>>
> Ok, I think I had missed that. You are saying that the
> #ifdef (__BIG_ENDIAN_BITFIELD) vs __LITTLE_ENDIAN_BITFIELD
>
> is only added to kernel-only data structures?
No, we *should* have used __BIG/LITTLE_ENDIAN_BITFIELD for the uapi
definition, but we forgot.
>> It's annoying that the bit numbers are different between LE & BE, but I
>> think it's too late to change that.
>>
> I agree.
>
>> So nothing should change in the branch_entry definition in the header.
>>
>> My comment on your patch was that adding the union with val, makes it
>> easier to misuse the bitfields, because now the values can be accessed
>> via the bitfields and also via val, but when using val you have to know
>> that the bit numbers differ between BE/LE.
>>
> Ok, I get it now. We do not need to expose val to user. This is added
> for kernel code convenience only.
Yeah. Putting the union with val in the uapi encourages userspace to
misuse val to bypass the bitfields, and that risks causing endian bugs.
> But if we keep it in kernel, that may break some other rules about
> uapi headers.
I don't follow what you mean there.
We could use #ifdef __KERNEL__ in the uapi header to make the union
kernel-only, see below, but it's pretty gross.
struct perf_branch_entry {
__u64 from;
__u64 to;
#ifdef __KERNEL__
union {
__u64 val; /* to make it easier to clear all fields */
struct {
#endif
__u64 mispred:1, /* target mispredicted */
predicted:1,/* target predicted */
in_tx:1, /* in transaction */
abort:1, /* transaction abort */
cycles:16, /* cycle count to last branch */
type:4, /* branch type */
reserved:40;
#ifdef __KERNEL__
};
};
#endif
};
If we just do the inline I suggested we can clear the flags in a single
source line, and the generated code seems fine too, eg:
static inline void clear_perf_branch_entry_flags(struct perf_branch_entry *e)
{
e->mispred = 0;
e->predicted = 0;
e->in_tx = 0;
e->abort = 0;
e->cycles = 0;
e->type = 0;
e->reserved = 0;
}
cheers
next prev parent reply other threads:[~2021-09-17 12:38 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-09 7:56 [PATCH v1 00/13] perf/x86/amd: Add AMD Fam19h Branch Sampling support Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 01/13] perf/core: add union to struct perf_branch_entry Stephane Eranian
2021-09-09 19:03 ` Peter Zijlstra
2021-09-10 12:09 ` Michael Ellerman
2021-09-10 14:16 ` Michael Ellerman
2021-09-15 6:03 ` Stephane Eranian
2021-09-17 6:37 ` Madhavan Srinivasan
2021-09-17 6:48 ` Stephane Eranian
2021-09-17 7:05 ` Michael Ellerman
2021-09-17 7:39 ` Stephane Eranian
2021-09-17 12:38 ` Michael Ellerman [this message]
2021-09-17 16:42 ` Stephane Eranian
2021-09-19 10:27 ` Michael Ellerman
2021-09-09 7:56 ` [PATCH v1 02/13] x86/cpufeatures: add AMD Fam19h Branch Sampling feature Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 03/13] perf/x86/amd: add AMD Fam19h Branch Sampling support Stephane Eranian
2021-09-09 10:44 ` kernel test robot
2021-09-09 15:33 ` kernel test robot
2021-09-09 7:56 ` [PATCH v1 04/13] perf/x86/amd: add branch-brs helper event for Fam19h BRS Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 05/13] perf/x86/amd: enable branch sampling priv level filtering Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 06/13] perf/x86/amd: add AMD branch sampling period adjustment Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 07/13] perf/core: add idle hooks Stephane Eranian
2021-09-09 9:15 ` Peter Zijlstra
2021-09-09 10:42 ` kernel test robot
2021-09-09 11:02 ` kernel test robot
2021-09-09 7:56 ` [PATCH v1 08/13] perf/x86/core: " Stephane Eranian
2021-09-09 9:16 ` Peter Zijlstra
2021-09-09 7:56 ` [PATCH v1 09/13] perf/x86/amd: add idle hooks for branch sampling Stephane Eranian
2021-09-09 9:20 ` Peter Zijlstra
2021-09-09 7:56 ` [PATCH v1 10/13] perf tools: add branch-brs as a new event Stephane Eranian
2021-09-09 7:56 ` [PATCH v1 11/13] perf tools: improve IBS error handling Stephane Eranian
2021-09-13 19:34 ` Arnaldo Carvalho de Melo
2021-10-04 21:57 ` Kim Phillips
2021-10-04 23:44 ` Arnaldo Carvalho de Melo
2021-09-09 7:56 ` [PATCH v1 12/13] perf tools: improve error handling of AMD Branch Sampling Stephane Eranian
2021-10-04 21:57 ` Kim Phillips
2021-09-09 7:57 ` [PATCH v1 13/13] perf report: add addr_from/addr_to sort dimensions Stephane Eranian
2021-09-09 8:55 ` [PATCH v1 00/13] perf/x86/amd: Add AMD Fam19h Branch Sampling support Peter Zijlstra
2021-09-15 5:55 ` Stephane Eranian
2021-09-15 9:04 ` Peter Zijlstra
2021-10-28 18:30 ` Stephane Eranian
2021-09-27 20:17 ` Song Liu
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