From: Thomas Gleixner <tglx@linutronix.de>
To: Andy Lutomirski <luto@kernel.org>,
Sohil Mehta <sohil.mehta@intel.com>,
the arch/x86 maintainers <x86@kernel.org>
Cc: Tony Luck <tony.luck@intel.com>,
Dave Hansen <dave.hansen@intel.com>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>, Jens Axboe <axboe@kernel.dk>,
Christian Brauner <christian@brauner.io>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Shuah Khan <shuah@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Jonathan Corbet <corbet@lwn.net>, Raj Ashok <ashok.raj@intel.com>,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
Gayatri Kammela <gayatri.kammela@intel.com>,
Zeng Guang <guang.zeng@intel.com>,
"Williams, Dan J" <dan.j.williams@intel.com>,
Randy E Witt <randy.e.witt@intel.com>,
"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
Ramesh Thomas <ramesh.thomas@intel.com>,
Linux API <linux-api@vger.kernel.org>,
linux-arch@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-kselftest@vger.kernel.org
Subject: Re: [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall
Date: Fri, 01 Oct 2021 23:29:07 +0200 [thread overview]
Message-ID: <875yug4eos.ffs@tglx> (raw)
In-Reply-To: <0364c572-4bc2-4538-8d65-485dbfa81f0d@www.fastmail.com>
On Fri, Oct 01 2021 at 08:13, Andy Lutomirski wrote:
> On Fri, Oct 1, 2021, at 2:56 AM, Thomas Gleixner wrote:
>> On Thu, Sep 30 2021 at 21:41, Andy Lutomirski wrote:
>>> On Thu, Sep 30, 2021, at 5:01 PM, Thomas Gleixner wrote:
>>
>>> Now that I read the docs some more, I'm seriously concerned about this
>>> XSAVE design. XSAVES with UINTR is destructive -- it clears UINV. If
>>> we actually use this, then the whole last_cpu "preserve the state in
>>> registers" optimization goes out the window. So does anything that
>>> happens to assume that merely saving the state doesn't destroy it on
>>> respectable modern CPUs XRSTORS will #GP if you XRSTORS twice, which
>>> makes me nervous and would need a serious audit of our XRSTORS paths.
>>
>> I have no idea what you are fantasizing about. You can XRSTORS five
>> times in a row as long as your XSTATE memory image is correct.
>
> I'm just reading TFM, which is some kind of dystopian fantasy.
>
> 11.8.2.4 XRSTORS
>
> Before restoring the user-interrupt state component, XRSTORS verifies
> that UINV is 0. If it is not, XRSTORS causes a general-protection
> fault (#GP) before loading any part of the user-interrupt state
> component. (UINV is IA32_UINTR_MISC[39:32]; XRSTORS does not check the
> contents of the remainder of that MSR.)
Duh. I was staring at the SDM and searching for a hint. Stupid me!
> So if UINV is set in the memory image and you XRSTORS five times in a
> row, the first one will work assuming UINV was zero. The second one
> will #GP.
Yes. I can see what you mean now :)
> 11.8.2.3 XSAVES
> After saving the user-interrupt state component, XSAVES clears UINV. (UINV is IA32_UINTR_MISC[39:32];
> XSAVES does not modify the remainder of that MSR.)
>
> So if we're running a UPID-enabled user task and we switch to a kernel
> thread, we do XSAVES and UINV is cleared. Then we switch back to the
> same task and don't do XRSTORS (or otherwise write IA32_UINTR_MISC)
> and UINV is still clear.
Yes, that has to be mopped up on the way to user space.
> And we had better clear UINV when running a kernel thread because the
> UPID might get freed or the kernel thread might do some CPL3
> shenanigans (via EFI, perhaps? I don't know if any firmwares actually
> do this).
Right. That's what happens already with the current pile.
> So all this seems to put UINV into the "independent" category of
> feature along with LBR. And the 512-byte wastes from extra copies of
> the legacy area and the loss of the XMODIFIED optimization will just
> be collateral damage.
So we'd end up with two XSAVES on context switch. We can simply do:
XSAVES();
fpu.state.xtsate.uintr.uinv = 0;
which allows to do as many XRSTORS in a row as we want. Only the final
one on the way to user space will have to restore the real vector if the
register state is not valid:
if (fpu_state_valid()) {
if (needs_uinv(current)
wrmsrl(UINV, vector);
} else {
if (needs_uinv(current)
fpu.state.xtsate.uintr.uinv = vector;
XRSTORS();
}
Hmm?
Thanks,
tglx
next prev parent reply other threads:[~2021-10-01 21:29 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 20:01 [RFC PATCH 00/13] x86 User Interrupts support Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 01/13] x86/uintr/man-page: Include man pages draft for reference Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 02/13] Documentation/x86: Add documentation for User Interrupts Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 03/13] x86/cpu: Enumerate User Interrupts support Sohil Mehta
2021-09-23 22:24 ` Thomas Gleixner
2021-09-24 19:59 ` Sohil Mehta
2021-09-27 20:42 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 04/13] x86/fpu/xstate: Enumerate User Interrupts supervisor state Sohil Mehta
2021-09-23 22:34 ` Thomas Gleixner
2021-09-27 22:25 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 05/13] x86/irq: Reserve a user IPI notification vector Sohil Mehta
2021-09-23 23:07 ` Thomas Gleixner
2021-09-25 13:30 ` Thomas Gleixner
2021-09-26 12:39 ` Thomas Gleixner
2021-09-27 19:07 ` Sohil Mehta
2021-09-28 8:11 ` Thomas Gleixner
2021-09-27 19:26 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 06/13] x86/uintr: Introduce uintr receiver syscalls Sohil Mehta
2021-09-23 12:26 ` Greg KH
2021-09-24 0:05 ` Thomas Gleixner
2021-09-27 23:20 ` Sohil Mehta
2021-09-28 4:39 ` Greg KH
2021-09-28 16:47 ` Sohil Mehta
2021-09-23 23:52 ` Thomas Gleixner
2021-09-27 23:57 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 07/13] x86/process/64: Add uintr task context switch support Sohil Mehta
2021-09-24 0:41 ` Thomas Gleixner
2021-09-28 0:30 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 08/13] x86/process/64: Clean up uintr task fork and exit paths Sohil Mehta
2021-09-24 1:02 ` Thomas Gleixner
2021-09-28 1:23 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 09/13] x86/uintr: Introduce vector registration and uintr_fd syscall Sohil Mehta
2021-09-24 10:33 ` Thomas Gleixner
2021-09-28 20:40 ` Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 10/13] x86/uintr: Introduce user IPI sender syscalls Sohil Mehta
2021-09-23 12:28 ` Greg KH
2021-09-28 18:01 ` Sohil Mehta
2021-09-29 7:04 ` Greg KH
2021-09-29 14:27 ` Sohil Mehta
2021-09-24 10:54 ` Thomas Gleixner
2021-09-13 20:01 ` [RFC PATCH 11/13] x86/uintr: Introduce uintr_wait() syscall Sohil Mehta
2021-09-24 11:04 ` Thomas Gleixner
2021-09-25 12:08 ` Thomas Gleixner
2021-09-28 23:13 ` Sohil Mehta
2021-09-28 23:08 ` Sohil Mehta
2021-09-26 14:41 ` Thomas Gleixner
2021-09-29 1:09 ` Sohil Mehta
2021-09-29 3:30 ` Andy Lutomirski
2021-09-29 4:56 ` Sohil Mehta
2021-09-30 18:08 ` Andy Lutomirski
2021-09-30 19:29 ` Thomas Gleixner
2021-09-30 22:01 ` Andy Lutomirski
2021-10-01 0:01 ` Thomas Gleixner
2021-10-01 4:41 ` Andy Lutomirski
2021-10-01 9:56 ` Thomas Gleixner
2021-10-01 15:13 ` Andy Lutomirski
2021-10-01 18:04 ` Sohil Mehta
2021-10-01 21:29 ` Thomas Gleixner [this message]
2021-10-01 23:00 ` Sohil Mehta
2021-10-01 23:04 ` Andy Lutomirski
2021-09-13 20:01 ` [RFC PATCH 12/13] x86/uintr: Wire up the user interrupt syscalls Sohil Mehta
2021-09-13 20:01 ` [RFC PATCH 13/13] selftests/x86: Add basic tests for User IPI Sohil Mehta
2021-09-13 20:27 ` [RFC PATCH 00/13] x86 User Interrupts support Dave Hansen
2021-09-14 19:03 ` Mehta, Sohil
2021-09-23 12:19 ` Greg KH
2021-09-23 14:09 ` Greg KH
2021-09-23 14:46 ` Dave Hansen
2021-09-23 15:07 ` Greg KH
2021-09-23 23:24 ` Sohil Mehta
2021-09-23 23:09 ` Sohil Mehta
2021-09-24 0:17 ` Sohil Mehta
2021-09-23 14:39 ` Jens Axboe
2021-09-29 4:31 ` Andy Lutomirski
2021-09-30 16:30 ` Stefan Hajnoczi
2021-09-30 17:24 ` Sohil Mehta
2021-09-30 17:26 ` Andy Lutomirski
2021-10-01 16:35 ` Stefan Hajnoczi
2021-10-01 16:41 ` Richard Henderson
2021-09-30 16:26 ` Stefan Hajnoczi
2021-10-01 0:40 ` Sohil Mehta
2021-10-01 8:19 ` Pavel Machek
2021-11-18 22:19 ` Sohil Mehta
2021-11-16 3:49 ` Prakash Sangappa
2021-11-18 21:44 ` Sohil Mehta
2021-12-22 16:17 ` Chrisma Pakha
2022-01-07 2:08 ` Sohil Mehta
2022-01-17 1:14 ` Chrisma Pakha
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