From: Thomas Gleixner <tglx@linutronix.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>, maz@kernel.org
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>, Huacai Chen <chenhc@lemote.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-mips@vger.kernel.org
Subject: Re: [PATCH v3 1/6] irqchip: Add Loongson HyperTransport Vector support
Date: Wed, 13 May 2020 14:06:54 +0200 [thread overview]
Message-ID: <87a72c3uox.fsf@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20200501092139.2988670-1-jiaxun.yang@flygoat.com>
Jiaxun Yang <jiaxun.yang@flygoat.com> writes:
> +static void htvec_mask_irq(struct irq_data *d)
> +{
> + struct htvec *priv = irq_data_get_irq_chip_data(d);
> + void __iomem *addr = priv->base + HTVEC_EN_OFF;
> + unsigned long flags;
> + u32 reg;
> +
> + raw_spin_lock_irqsave(&priv->htvec_lock, flags);
No need for irqsave() these functions are called with interrupts disabled.
> + addr += VEC_REG_IDX(d->hwirq) * 4;
> + reg = readl(addr);
> + reg &= ~BIT(VEC_REG_BIT(d->hwirq));
> + writel(reg, addr);
> + raw_spin_unlock_irqrestore(&priv->htvec_lock, flags);
> +}
> +static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *arg)
> +{
> + struct htvec *priv = domain->host_data;
> + unsigned long hwirq;
> + unsigned int type, i;
> +
> + irq_domain_translate_onecell(domain, arg, &hwirq, &type);
> +
> + for (i = 0; i < nr_irqs; i++)
> + irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
> + priv, handle_edge_irq, NULL, NULL);
This wants curly brackets and the second line of arguments wants to be
aligned with the first argument:
for (i = 0; i < nr_irqs; i++) {
irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
priv, handle_edge_irq, NULL, NULL);
}
See https://lore.kernel.org/lkml/alpine.DEB.2.20.1701171956290.3645@nanos/
The alignment of arguments wants to be fixed all over the place.
> +static int htvec_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + struct htvec *priv;
> + int err, parent_irq[4], num_parents = 0, i;
Please order the variable declaration in reverse fir tree length order:
int err, parent_irq[4], num_parents = 0, i;
struct htvec *priv;
That's way better readable than the above. All over the place please.
> + priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
> + VEC_COUNT,
> + &htvec_domain_ops,
> + priv);
> + if (!priv->htvec_domain) {
> + pr_err("Failed to create IRQ domain\n");
> + err = -ENOMEM;
> + goto iounmap_base;
> + }
> +
> + htvec_reset(priv);
> +
> + for (i = 0; i < num_parents; i++)
> + irq_set_chained_handler_and_data(parent_irq[i],
> + htvec_irq_dispatch, priv);
See above.
Thanks,
tglx
prev parent reply other threads:[~2020-05-13 12:07 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-22 14:24 [PATCH 0/6] Loongson PCH IRQ Support Jiaxun Yang
2020-04-22 14:24 ` [PATCH 1/6] irqchip: Add Loongson HyperTransport Vector support Jiaxun Yang
2020-04-23 13:31 ` Marc Zyngier
2020-04-22 14:24 ` [PATCH 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Jiaxun Yang
2020-04-22 14:24 ` [PATCH 3/6] irqchip: Add Loongson PCH PIC controller Jiaxun Yang
2020-04-23 5:56 ` Huacai Chen
2020-04-23 14:23 ` Marc Zyngier
2020-04-22 14:24 ` [PATCH 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC Jiaxun Yang
2020-04-23 5:54 ` Huacai Chen
2020-04-22 14:24 ` [PATCH 5/6] irqchip: Add Loongson PCH MSI controller Jiaxun Yang
2020-04-23 5:57 ` Huacai Chen
2020-04-23 14:41 ` Marc Zyngier
2020-04-24 1:33 ` Jiaxun Yang
2020-04-24 8:28 ` Marc Zyngier
2020-04-22 14:24 ` [PATCH 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Jiaxun Yang
2020-04-23 5:55 ` Huacai Chen
2020-04-23 12:43 ` Marc Zyngier
2020-04-24 1:27 ` Huacai Chen
2020-04-23 5:50 ` [PATCH 0/6] Loongson PCH IRQ Support Huacai Chen
2020-04-28 6:32 ` [PATCH v2 1/6] irqchip: Add Loongson HyperTransport Vector support Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 3/6] irqchip: Add Loongson PCH PIC controller Jiaxun Yang
2020-05-13 12:09 ` Thomas Gleixner
2020-04-28 6:32 ` [PATCH v2 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 5/6] irqchip: Add Loongson PCH MSI controller Jiaxun Yang
2020-04-28 13:07 ` Marc Zyngier
2020-05-13 12:13 ` Thomas Gleixner
2020-05-13 12:15 ` Thomas Gleixner
2020-05-20 11:51 ` Jiaxun Yang
2020-04-28 6:32 ` [PATCH v2 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Jiaxun Yang
2020-04-28 16:59 ` [PATCH v2 1/6] irqchip: Add Loongson HyperTransport Vector support Marc Zyngier
2020-05-01 9:21 ` [PATCH v3 " Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC Jiaxun Yang
2020-05-12 16:42 ` Rob Herring
2020-05-01 9:21 ` [PATCH v3 3/6] irqchip: Add Loongson PCH PIC controller Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 4/6] dt-bindings: interrupt-controller: Add Loongson PCH PIC Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 5/6] irqchip: Add Loongson PCH MSI controller Jiaxun Yang
2020-05-01 9:21 ` [PATCH v3 6/6] dt-bindings: interrupt-controller: Add Loongson PCH MSI Jiaxun Yang
2020-05-12 20:57 ` Rob Herring
2020-05-12 7:45 ` [PATCH v3 1/6] irqchip: Add Loongson HyperTransport Vector support Jiaxun Yang
2020-05-13 12:06 ` Thomas Gleixner [this message]
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