From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86EA8C04FF3 for ; Mon, 24 May 2021 15:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67A96613F2 for ; Mon, 24 May 2021 15:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233265AbhEXP0b convert rfc822-to-8bit (ORCPT ); Mon, 24 May 2021 11:26:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:46992 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233126AbhEXPXM (ORCPT ); Mon, 24 May 2021 11:23:12 -0400 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7DEF5613DF; Mon, 24 May 2021 15:21:44 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1llCOk-003Fit-CT; Mon, 24 May 2021 16:21:42 +0100 Date: Mon, 24 May 2021 16:21:41 +0100 Message-ID: <87fsycw41m.wl-maz@kernel.org> From: Marc Zyngier To: Andreas =?UTF-8?B?RsOkcmJlcg==?= Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Heiko Stuebner , devicetree@vger.kernel.org Subject: Re: [PATCH 3/9] arm64: dts: rockchip: Prepare Rockchip RK1808 In-Reply-To: <7ef183f1-00f8-13c4-1fd3-eae9e0bbf74c@suse.de> References: <20210516230551.12469-1-afaerber@suse.de> <20210516230551.12469-4-afaerber@suse.de> <87h7j1vhq7.wl-maz@kernel.org> <7ef183f1-00f8-13c4-1fd3-eae9e0bbf74c@suse.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: afaerber@suse.de, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 24 May 2021 14:32:41 +0100, Andreas Färber wrote: > > On 17.05.21 11:21, Marc Zyngier wrote: > > On Mon, 17 May 2021 00:05:45 +0100, > > Andreas Färber wrote: > >> > >> Add an initial Device Tree for Rockchip RK1808 SoC. > >> Based on shipping TB-RK1808M0 DTB. > >> > >> Signed-off-by: Andreas Färber > >> --- > >> arch/arm64/boot/dts/rockchip/rk1808.dtsi | 203 +++++++++++++++++++++++ > >> 1 file changed, 203 insertions(+) > >> create mode 100644 arch/arm64/boot/dts/rockchip/rk1808.dtsi > >> > >> diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi > >> new file mode 100644 > >> index 000000000000..af2b51afda7d > >> --- /dev/null > >> +++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi > [...] > >> + gic: interrupt-controller@ff100000 { > >> + compatible = "arm,gic-v3"; > >> + reg = <0xff100000 0x10000>, /* GICD */ > >> + <0xff140000 0xc0000>, /* GICR */ > > > > This is obviously wrong. You have two CPUs, and yet describe a range > > that spans 6. I guess this is a copy paste from rk3399 again? > > Not on my part at least. As indicated, these numbers are what ships in > the DTB on the RK1808 card, as per dtc -I dtb -O dts. Could be a mistake > by Rockchip, of course. > > Are you suggesting 0xc0000/6*2 = 0x40000 for two CPUs here? Works > as bad as before - investigation still ongoing with latest next. > > As for "obviously": The GICv3 YAML binding has no description for me to > validate those numbers: "GIC Redistributors (GICR), one range per > redistributor region" - says nothing about correlation to number of CPUs > or size per CPU, and the examples are not explaining either: 0x200000 > has no number of CPUs associated, and by my calculation 0x800000 for 32 > CPUs results in 0x40000 per CPU; but then again the examples also have > GICC etc. at diverging 0x2000 size. The GICv3/v4 architecture spec does apply, and you should really have a look at what these sizes mean. What is the value of copy-pasting things without understanding it the first place? > > >> + <0xff300000 0x10000>, /* GICC */ > >> + <0xff310000 0x10000>, /* GICH */ > >> + <0xff320000 0x10000>; /* GICV */ > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + interrupts = ; > >> + #address-cells = <1>; > >> + #size-cells = <1>; > >> + ranges; > >> + > >> + gic_its: msi-controller@ff120000 { > >> + compatible = "arm,gic-v3-its"; > >> + reg = <0xff120000 0x20000>; > >> + msi-controller; > >> + #msi-cells = <1>; > >> + }; > > > > What uses the ITS? > > DT-wise seemingly only the __symbols__ table (named just "its" there, I > notice), so we could drop (or rename) the label if you prefer. No, I am asking *what* uses the ITS. Is it just dangling without any user? No PCI bus making use of it? M. -- Without deviation from the norm, progress is not possible.