From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, catalin.marinas@arm.com,
mathieu.poirier@linaro.org, mike.leach@linaro.org,
leo.yan@linaro.org, anshuman.khandual@arm.com,
coresight@lists.linaro.org, maz@kernel.org, james.morse@arm.com,
mark.rutland@arm.com, lcherian@marvell.com
Subject: Re: [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures
Date: Mon, 11 Oct 2021 13:32:40 +0100 [thread overview]
Message-ID: <982da86b-44ff-b244-33b0-02c95fa2f082@arm.com> (raw)
In-Reply-To: <20211011101851.GC3681@willie-the-truck>
On 11/10/2021 11:18, Will Deacon wrote:
> On Fri, Oct 08, 2021 at 07:29:05PM +0100, Suzuki K Poulose wrote:
>> Advertise the workaround for the TSB flush failures via
>> Kconfig entries.
>>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> Changes since previous:
>> - Split the Kconfig/erratum updates to keep the conflicts
>> minimal with the other Kconfig updates in TRBE errata
>> I have retained the tags
>> ---
>> Documentation/arm64/silicon-errata.rst | 4 ++++
>> arch/arm64/Kconfig | 31 ++++++++++++++++++++++++++
>> 2 files changed, 35 insertions(+)
>>
>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
>> index 2f99229d993c..569a92411dcd 100644
>> --- a/Documentation/arm64/silicon-errata.rst
>> +++ b/Documentation/arm64/silicon-errata.rst
>> @@ -94,6 +94,8 @@ stable kernels.
>> +----------------+-----------------+-----------------+-----------------------------+
>> | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
>> +----------------+-----------------+-----------------+-----------------------------+
>> +| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
>> ++----------------+-----------------+-----------------+-----------------------------+
>> | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
>> +----------------+-----------------+-----------------+-----------------------------+
>> | ARM | Neoverse-N1 | #1349291 | N/A |
>> @@ -102,6 +104,8 @@ stable kernels.
>> +----------------+-----------------+-----------------+-----------------------------+
>> | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
>> +----------------+-----------------+-----------------+-----------------------------+
>> +| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
>> ++----------------+-----------------+-----------------+-----------------------------+
>> | ARM | MMU-500 | #841119,826419 | N/A |
>> +----------------+-----------------+-----------------+-----------------------------+
>> +----------------+-----------------+-----------------+-----------------------------+
>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>> index eac4030322df..0764774e12bb 100644
>> --- a/arch/arm64/Kconfig
>> +++ b/arch/arm64/Kconfig
>> @@ -705,6 +705,37 @@ config ARM64_ERRATUM_2139208
>>
>> If unsure, say Y.
>>
>> +config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
>> + bool
>> +
>> +config ARM64_ERRATUM_2054223
>> + bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
>> + default y
>> + help
>> + Enable workaround for ARM Cortex-A710 erratum 2054223
>> +
>> + Affected cores may fail to flush the trace data on a TSB instruction, when
>> + the PE is in trace prohibited state. This will cause losing a few bytes
>> + of the trace cached.
>> +
>> + Workaround is to issue two TSB consecutively on affected cores.
>> +
>> + If unsure, say Y.
>> +
>> +config ARM64_ERRATUM_2067961
>> + bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
>> + default y
>> + help
>> + Enable workaround for ARM Neoverse-N2 erratum 2067961
>> +
>> + Affected cores may fail to flush the trace data on a TSB instruction, when
>> + the PE is in trace prohibited state. This will cause losing a few bytes
>> + of the trace cached.
>> +
>> + Workaround is to issue two TSB consecutively on affected cores.
>> +
>> + If unsure, say Y.
>
> Shouldn't these two be selecting the workaround?
doh! I have given myself a slap for this and fixed it locally.
Suzuki
next prev parent reply other threads:[~2021-10-11 12:32 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-08 18:28 [PATCH v3 00/16] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 01/16] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 02/16] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 03/16] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-11 10:20 ` Will Deacon
2021-10-08 18:28 ` [PATCH v3 04/16] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 05/16] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 06/16] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 07/16] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 08/16] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 09/16] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 10/16] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 11/16] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 12/16] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 13/16] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 14/16] arm64: errata: Advertise workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures Suzuki K Poulose
2021-10-11 10:18 ` Will Deacon
2021-10-11 12:32 ` Suzuki K Poulose [this message]
2021-10-08 18:29 ` [PATCH v3 16/16] arm64: errata: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
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