From: "D, Lakshmi Sowjanya" <lakshmi.sowjanya.d@intel.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
"Raja Subramanian,
Lakshmi Bai" <lakshmi.bai.raja.subramanian@intel.com>,
"Saha, Tamal" <tamal.saha@intel.com>
Subject: RE: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver
Date: Fri, 30 Jul 2021 11:06:00 +0000 [thread overview]
Message-ID: <BL3PR11MB569935231C507843CBE0370EC4EC9@BL3PR11MB5699.namprd11.prod.outlook.com> (raw)
In-Reply-To: <CACRpkdZJaoQEJsAqrrAxWcpgx6J0OGoc_CkP0kUdNe-RPkRvqA@mail.gmail.com>
Thank you Linus Walleij !!
I'll include the same and post the next version with 'Reviewed-by: Linus Walleij <linus.walleij@linaro.org>' tag.
Thanks and Regards,
Lakshmi Sowjanya
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Friday, July 30, 2021 2:45 PM
> To: D, Lakshmi Sowjanya <lakshmi.sowjanya.d@intel.com>
> Cc: open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>; linux-kernel
> <linux-kernel@vger.kernel.org>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; Raja Subramanian, Lakshmi Bai
> <lakshmi.bai.raja.subramanian@intel.com>; Saha, Tamal
> <tamal.saha@intel.com>
> Subject: Re: [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel
> Keembay pinctrl driver
>
> On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote:
>
> > From: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
> >
> > Add Device Tree bindings documentation for Intel Keem Bay SoC's pin
> > controller.
> > Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file
> >
> > Acked-by: Mark Gross <mgross@linux.intel.com>
> > Co-developed-by: Vineetha G. Jaya Kumaran
> > <vineetha.g.jaya.kumaran@intel.com>
> > Signed-off-by: Vineetha G. Jaya Kumaran
> > <vineetha.g.jaya.kumaran@intel.com>
> > Co-developed-by: Vijayakannan Ayyathurai
> > <vijayakannan.ayyathurai@intel.com>
> > Signed-off-by: Vijayakannan Ayyathurai
> > <vijayakannan.ayyathurai@intel.com>
> > Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
> (...)
> > + interrupts:
> > + description:
> > + Specifies the interrupt lines to be used by the controller.
> > + maxItems: 8
>
> Write here that each interrupt is shared by up to 4 GPIO lines.
>
> With that:
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
next prev parent reply other threads:[~2021-07-30 11:06 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 16:27 [PATCH v3 0/2] Add pinctrl support for Intel Keem Bay SoC lakshmi.sowjanya.d
2021-07-16 16:27 ` [PATCH v3 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver lakshmi.sowjanya.d
2021-07-30 9:05 ` Linus Walleij
2021-07-30 11:29 ` Andy Shevchenko
2021-07-30 11:58 ` Linus Walleij
2021-07-30 9:15 ` Linus Walleij
2021-07-30 11:06 ` D, Lakshmi Sowjanya [this message]
2021-07-16 16:27 ` [PATCH v3 2/2] pinctrl: Add Intel Keem Bay " lakshmi.sowjanya.d
2021-07-28 19:16 ` [kbuild] " Dan Carpenter
2021-07-30 11:05 ` D, Lakshmi Sowjanya
2021-07-30 9:13 ` Linus Walleij
2021-07-30 9:32 ` Andy Shevchenko
2021-07-30 11:06 ` D, Lakshmi Sowjanya
2021-07-30 11:30 ` Andy Shevchenko
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