From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Yongqiang Niu <yongqiang.niu@mediatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Jassi Brar <jassisinghbrar@gmail.com>,
Fabien Parent <fparent@baylibre.com>,
Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>,
DTML <devicetree@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
DRI Development <dri-devel@lists.freedesktop.org>,
Project_Global_Chrome_Upstream_Group@mediatek.com,
Hsin-Yi Wang <hsinyi@chromium.org>
Subject: Re: [PATCH v3] drm/mediatek: adjust rdma fifo threshold calculate formula
Date: Mon, 12 Jul 2021 22:47:18 +0800 [thread overview]
Message-ID: <CAAOTY_-15k_Fq4svKfaKukuYxc4DRfqP1kRudR9wgSrkc-+ZoQ@mail.gmail.com> (raw)
In-Reply-To: <1625986431-27399-2-git-send-email-yongqiang.niu@mediatek.com>
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年7月11日 週日 下午2:54寫道:
>
> the orginal formula will caused rdma fifo threshold config overflow
> and no one could come out a solution for all SoC,
> set threshold to 70% of max fifo size to make sure it will
> not overflow, and 70% is a empirical value
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index f123fc0..f1f6a2e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -164,10 +164,10 @@ void mtk_rdma_config(struct device *dev, unsigned int width,
> /*
> * Enable FIFO underflow since DSI and DPI can't be blocked.
> * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> - * output threshold to 6 microseconds with 7/6 overhead to
> - * account for blanking, and with a pixel depth of 4 bytes:
> + * output threshold to 70% of max fifo size to make sure the
> + * threhold will not overflow
> */
> - threshold = width * height * vrefresh * 4 * 7 / 1000000;
> + threshold = rdma_fifo_size * 7 / 10;
> reg = RDMA_FIFO_UNDERFLOW_EN |
> RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> --
> 1.8.1.1.dirty
>
prev parent reply other threads:[~2021-07-12 14:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-11 6:53 [PATCHi v3] drm/mediatek: adjust rdma fifo threshold calculate formula Yongqiang Niu
2021-07-11 6:53 ` [PATCH " Yongqiang Niu
2021-07-12 14:47 ` Chun-Kuang Hu [this message]
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