From: Aaron Durbin <adurbin@chromium.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Daniel Kurtz <djkurtz@chromium.org>,
Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>,
Aaron Durbin <adurbin@chromium.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jslaby@suse.com>,
Marc Gonzalez <marc_gonzalez@sigmadesigns.com>,
Doug Anderson <dianders@chromium.org>,
Matt Redfearn <matt.redfearn@mips.com>,
Jeffy <jeffy.chen@rock-chips.com>,
"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] serial: 8250_early: Add earlycon support for AMD Carrizo / Stoneyridge
Date: Wed, 14 Mar 2018 11:09:58 -0600 [thread overview]
Message-ID: <CAE2855u0NhRNkwuro74HvNZdhLD+Fh+C8DkNXWMc88AK7UNu1w@mail.gmail.com> (raw)
In-Reply-To: <CAHp75VehhNv6pPrRiM9jBAK9FsqZ2Defo8HKhutwn+GPnCFp3w@mail.gmail.com>
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On Wed, Mar 14, 2018 at 10:38 AM, Andy Shevchenko <andy.shevchenko@gmail.com
> wrote:
> On Wed, Mar 14, 2018 at 6:29 PM, Daniel Kurtz <djkurtz@chromium.org>
> wrote:
> > On Wed, Mar 14, 2018 at 4:54 AM Ricardo Ribalda Delgado <
> > ricardo.ribalda@gmail.com> wrote:
> >> On Wed, Mar 14, 2018 at 1:36 AM, Daniel Kurtz <djkurtz@chromium.org>
> > wrote:
>
> > In fact, the recommended way is to have firmware specify an ACPI SPCR
> table
> > with OEMID="AMDCZ " (see https://patchwork.kernel.org/patch/10281307/)
> to
> > configure proper access and address.
>
> Hmm... I was thinking it's already there. And thus, this is just a
> quirk for *existing* firmware that doesn't correctly configured
> hardware.
> (Yes, I'm aware about one nuance in SPCR specification I'm trying to
> address via official ways)
>
What is "it's" in your first sentence? The access method? Baud rate can't
be configured ever in the kernel w/o knowing the input clock to the uart
block. That's already been brought up, and it is inherently a requirement
to know that to recalculate the divisor. These patches are doing early OOB
binding to set the proper input clock because: 1. SPCR doesn't have that
information 2. you nak'd the generic way of specifying the input clock on
the command line. Sadly, this situation is not unique to this hardware.
There is hardware all over that does not meet the current assumptions being
made in the early uart drivers within the kernel.
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next prev parent reply other threads:[~2018-03-14 17:09 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20180314003655.12141-1-djkurtz@chromium.org>
2018-03-14 0:36 ` [PATCH 1/3] serial: 8250_early: Add earlycon support for AMD Carrizo / Stoneyridge Daniel Kurtz
2018-03-14 10:35 ` Andy Shevchenko
2018-03-14 10:53 ` Ricardo Ribalda Delgado
2018-03-14 16:29 ` Daniel Kurtz
2018-03-14 16:38 ` Andy Shevchenko
2018-03-14 17:09 ` Aaron Durbin [this message]
2018-03-14 17:12 ` Aaron Durbin
2018-03-14 17:31 ` Andy Shevchenko
2018-03-26 18:24 ` Alan Cox
2018-03-27 2:56 ` Aaron Durbin
2018-03-29 13:34 ` Alan Cox
2018-04-01 18:54 ` Aaron Durbin
2018-04-06 13:47 ` Alan Cox
2018-04-09 16:00 ` Aaron Durbin
2018-03-14 0:36 ` [PATCH 2/3] ACPI: SPCR: Add support for AMD CT/SZ Daniel Kurtz
2018-03-14 10:36 ` Andy Shevchenko
2018-04-17 0:43 ` Jon Masters
2018-03-14 0:36 ` [PATCH 3/3] serial: core: Allow skipping old serial port initialization Daniel Kurtz
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