From: Evan Green <evgreen@chromium.org>
To: vnkgutta@codeaurora.org
Cc: robh@kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org, Andy Gross <andy.gross@linaro.org>,
David Brown <david.brown@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
devicetree@vger.kernel.org, tsoni@codeaurora.org,
ckadabi@codeaurora.org, rishabhb@codeaurora.org, bp@alien8.de
Subject: Re: [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver
Date: Fri, 10 Aug 2018 10:21:14 -0700 [thread overview]
Message-ID: <CAE=gft4zc8vHt_O0dTomu=3zq-_ri52WnjH=F6BhyaNoybu2hQ@mail.gmail.com> (raw)
In-Reply-To: <1533155615-27929-3-git-send-email-vnkgutta@codeaurora.org>
On Wed, Aug 1, 2018 at 1:33 PM Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org> wrote:
>
> Cache error reporting controller is to detect and report single
> and double bit errors on Last Level Cache Controller (LLCC) cache.
> Add required support to register LLCC EDAC driver as platform driver,
> from LLCC driver.
>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> ---
> drivers/soc/qcom/llcc-slice.c | 18 ++++++++++++++++--
> include/linux/soc/qcom/llcc-qcom.h | 2 ++
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
> index a63640d..09c8bb0 100644
> --- a/drivers/soc/qcom/llcc-slice.c
> +++ b/drivers/soc/qcom/llcc-slice.c
> @@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
> u32 attr0_val;
> u32 max_cap_cacheline;
> u32 sz;
> - int ret;
> + int ret = 0;
> const struct llcc_slice_config *llcc_table;
> struct llcc_slice_desc desc;
>
> @@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
> struct resource *llcc_banks_res, *llcc_bcast_res;
> void __iomem *llcc_banks_base, *llcc_bcast_base;
> int ret, i;
> + struct platform_device *llcc_edac;
>
> drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
> if (!drv_data)
> @@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
> mutex_init(&drv_data->lock);
> platform_set_drvdata(pdev, drv_data);
>
> - return qcom_llcc_cfg_program(pdev);
> + ret = qcom_llcc_cfg_program(pdev);
> + if (ret)
> + return ret;
> +
> + drv_data->ecc_irq = platform_get_irq(pdev, 0);
> + if (drv_data->ecc_irq >= 0) {
This condition will always be true for u32. See below...
> + llcc_edac = platform_device_register_data(&pdev->dev,
> + "qcom_llcc_edac", -1, drv_data,
> + sizeof(*drv_data));
> + if (IS_ERR(llcc_edac))
> + dev_err(dev, "Failed to register llcc edac driver\n");
> + }
> +
> + return ret;
> }
> EXPORT_SYMBOL_GPL(qcom_llcc_probe);
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index c681e79..1a3bc25 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -78,6 +78,7 @@ struct llcc_slice_config {
> * @num_banks: Number of llcc banks
> * @bitmap: Bit map to track the active slice ids
> * @offsets: Pointer to the bank offsets array
> + * @ecc_irq: interrupt for llcc cache error detection and reporting
> */
> struct llcc_drv_data {
> struct regmap *regmap;
> @@ -89,6 +90,7 @@ struct llcc_drv_data {
> u32 num_banks;
> unsigned long *bitmap;
> u32 *offsets;
> + u32 ecc_irq;
The return type for platform_get_irq is int, so this should probably
be int, or "unsigned", but then you'd need to fix your logic above.
> };
>
> #if IS_ENABLED(CONFIG_QCOM_LLCC)
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
next prev parent reply other threads:[~2018-08-10 17:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-01 20:33 [PATCH v1 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-01 20:33 ` [PATCH v1 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
2018-08-01 20:33 ` [PATCH v1 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
2018-08-10 17:21 ` Evan Green [this message]
2018-08-10 23:04 ` vnkgutta
2018-08-01 20:33 ` [PATCH v1 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-08 23:11 ` vnkgutta
2018-08-10 3:59 ` Borislav Petkov
2018-08-10 23:03 ` vnkgutta
2018-08-10 17:23 ` Evan Green
2018-08-10 23:13 ` vnkgutta
2018-08-11 0:14 ` Evan Green
2018-08-01 20:33 ` [PATCH v1 4/4] dt-bindigs: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAE=gft4zc8vHt_O0dTomu=3zq-_ri52WnjH=F6BhyaNoybu2hQ@mail.gmail.com' \
--to=evgreen@chromium.org \
--cc=andy.gross@linaro.org \
--cc=bp@alien8.de \
--cc=ckadabi@codeaurora.org \
--cc=david.brown@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-edac@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-soc@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mchehab@kernel.org \
--cc=rishabhb@codeaurora.org \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
--cc=tsoni@codeaurora.org \
--cc=vnkgutta@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).