From: Guo Ren <guoren@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv <linux-riscv@lists.infradead.org>,
devicetree <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>, Wei Fu <wefu@redhat.com>,
liush <liush@allwinnertech.com>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
Drew Fustini <drew@beagleboard.org>,
Christoph Hellwig <hch@lst.de>, Arnd Bergmann <arnd@arndb.de>,
Chen-Yu Tsai <wens@csie.org>, Maxime Ripard <maxime@cerno.tech>,
Greg Favor <gfavor@ventanamicro.com>,
Andrea Mondelli <andrea.mondelli@huawei.com>,
Jonathan Behrens <behrensj@mit.edu>,
"Xinhaoqu (Freddie)" <xinhaoqu@huawei.com>,
Bill Huffman <huffman@cadence.com>,
Nick Kossifidis <mick@ics.forth.gr>,
Allen Baum <allen.baum@esperantotech.com>,
Josh Scheid <jscheid@ventanamicro.com>,
Richard Trauben <rtrauben@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Christoph Muellner <cmuellner@linux.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: Re: [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types
Date: Wed, 9 Mar 2022 15:56:31 +0800 [thread overview]
Message-ID: <CAJF2gTRRF-=GCsRRm5+JZ=uHXSX=mwE0anQsRtRXEDPPBkDB7w@mail.gmail.com> (raw)
In-Reply-To: <20220209123800.269774-1-heiko@sntech.de>
After trying it on my SMP 4*910 platform, it could boot normally.
Tested-by: Guo Ren <guoren@kernel.org>
On Wed, Feb 9, 2022 at 8:38 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> Svpbmt is an extension defining "Supervisor-mode: page-based memory types"
> for things like non-cacheable pages or I/O memory pages.
>
>
> So this is my 2nd try at implementing Svpbmt (and the diverging D1 memory
> types) using the alternatives framework.
>
> This includes a number of changes to the alternatives mechanism itself.
> The biggest one being the move to a more central location, as I expect
> in the future, nearly every chip needing some sort of patching, be it
> either for erratas or for optional features (svpbmt or others).
>
> The dt-binding for svpbmt itself is of course not finished and is still
> using the binding introduced in previous versions, as where to put
> a svpbmt-property in the devicetree is still under dicussion.
> Atish seems to be working on a framework for extensions [0],
>
> The series also introduces support for the memory types of the D1
> which are implemented differently to svpbmt. But when patching anyway
> it's pretty clean to add the D1 variant via ALTERNATIVE_2 to the same
> location.
>
> The only slightly bigger difference is that the "normal" type is not 0
> as with svpbmt, so kernel patches for this PMA type need to be applied
> even before the MMU is brought up, so the series introduces a separate
> stage for that.
>
>
> In theory this series is 3 parts:
> - sbi cache-flush / null-ptr
> - alternatives improvements
> - svpbmt+d1
>
> So expecially patches from the first 2 areas could be applied when
> deemed ready, I just thought to keep it together to show-case where
> the end-goal is and not requiring jumping between different series.
>
>
> The sbi cache-flush patch is based on Atish's sparse-hartid patch [1],
> as it touches a similar area in mm/cacheflush.c
>
>
> I picked the recipient list from the previous version, hopefully
> I didn't forget anybody.
>
> changes in v6:
> - rebase onto 5.17-rc1
> - handle sbi null-ptr differently
> - improve commit messages
> - use riscv,mmu as property name
>
> changes in v5:
> - move to use alternatives for runtime-patching
> - add D1 variant
>
>
> [0] https://lore.kernel.org/r/20211224211632.1698523-1-atishp@rivosinc.com
> [1] https://lore.kernel.org/r/20220120090918.2646626-1-atishp@rivosinc.com
>
>
> Heiko Stuebner (12):
> riscv: prevent null-pointer dereference with sbi_remote_fence_i
> riscv: integrate alternatives better into the main architecture
> riscv: allow different stages with alternatives
> riscv: implement module alternatives
> riscv: implement ALTERNATIVE_2 macro
> riscv: extend concatenated alternatives-lines to the same length
> riscv: prevent compressed instructions in alternatives
> riscv: move boot alternatives to a slightly earlier position
> riscv: Fix accessing pfn bits in PTEs for non-32bit variants
> riscv: add cpufeature handling via alternatives
> riscv: remove FIXMAP_PAGE_IO and fall back to its default value
> riscv: add memory-type errata for T-Head
>
> Wei Fu (2):
> dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt
> riscv: add RISC-V Svpbmt extension support
>
> .../devicetree/bindings/riscv/cpus.yaml | 10 ++
> arch/riscv/Kconfig.erratas | 29 ++--
> arch/riscv/Kconfig.socs | 1 -
> arch/riscv/Makefile | 2 +-
> arch/riscv/errata/Makefile | 2 +-
> arch/riscv/errata/sifive/errata.c | 10 +-
> arch/riscv/errata/thead/Makefile | 1 +
> arch/riscv/errata/thead/errata.c | 85 +++++++++++
> arch/riscv/include/asm/alternative-macros.h | 114 ++++++++-------
> arch/riscv/include/asm/alternative.h | 16 ++-
> arch/riscv/include/asm/errata_list.h | 52 +++++++
> arch/riscv/include/asm/fixmap.h | 2 -
> arch/riscv/include/asm/pgtable-32.h | 17 +++
> arch/riscv/include/asm/pgtable-64.h | 79 +++++++++-
> arch/riscv/include/asm/pgtable-bits.h | 10 --
> arch/riscv/include/asm/pgtable.h | 53 +++++--
> arch/riscv/include/asm/vendorid_list.h | 1 +
> arch/riscv/kernel/Makefile | 1 +
> arch/riscv/{errata => kernel}/alternative.c | 48 ++++++-
> arch/riscv/kernel/cpufeature.c | 136 +++++++++++++++++-
> arch/riscv/kernel/head.S | 2 +
> arch/riscv/kernel/module.c | 29 ++++
> arch/riscv/kernel/sbi.c | 10 +-
> arch/riscv/kernel/smpboot.c | 4 -
> arch/riscv/kernel/traps.c | 2 +-
> arch/riscv/mm/init.c | 1 +
> 26 files changed, 606 insertions(+), 111 deletions(-)
> create mode 100644 arch/riscv/errata/thead/Makefile
> create mode 100644 arch/riscv/errata/thead/errata.c
> rename arch/riscv/{errata => kernel}/alternative.c (59%)
>
> --
> 2.30.2
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
prev parent reply other threads:[~2022-03-09 7:58 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 12:37 [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i Heiko Stuebner
2022-02-11 1:59 ` Atish Patra
2022-02-09 12:37 ` [PATCH v6 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 03/14] riscv: allow different stages with alternatives Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 04/14] riscv: implement module alternatives Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-03-08 0:47 ` Palmer Dabbelt
2022-02-09 12:37 ` [PATCH v6 08/14] riscv: move boot alternatives to a slightly earlier position Heiko Stuebner
2022-02-10 22:42 ` Atish Patra
2022-02-11 1:11 ` Heiko Stübner
2022-02-11 1:57 ` Atish Patra
2022-02-11 9:34 ` Heiko Stübner
2022-03-08 0:47 ` Palmer Dabbelt
2022-03-23 16:51 ` Heiko Stübner
2022-02-09 12:37 ` [PATCH v6 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt Heiko Stuebner
2022-02-09 18:47 ` Rob Herring
2022-02-09 12:37 ` [PATCH v6 12/14] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-02-09 12:37 ` [PATCH v6 13/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-02-09 12:38 ` [PATCH v6 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-02-11 0:12 ` Atish Patra
2022-02-11 9:25 ` Heiko Stübner
2022-02-12 0:27 ` Atish Patra
2022-02-11 2:01 ` Atish Patra
2022-02-14 3:42 ` Samuel Holland
2022-02-09 17:49 ` [PATCH v6 00/14] riscv: support for Svpbmt and D1 memory types Jisheng Zhang
2022-02-09 23:44 ` Heiko Stübner
2022-02-10 16:01 ` Jisheng Zhang
2022-02-11 0:25 ` Atish Patra
2022-02-11 1:48 ` Atish Patra
2022-02-11 2:04 ` Heiko Stübner
2022-02-12 0:25 ` Atish Patra
2022-02-14 20:02 ` Heiko Stübner
2022-02-14 20:25 ` Atish Patra
2022-02-14 20:37 ` Heiko Stübner
2022-03-09 7:56 ` Guo Ren [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAJF2gTRRF-=GCsRRm5+JZ=uHXSX=mwE0anQsRtRXEDPPBkDB7w@mail.gmail.com' \
--to=guoren@kernel.org \
--cc=allen.baum@esperantotech.com \
--cc=andrea.mondelli@huawei.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=arnd@arndb.de \
--cc=atishp@atishpatra.org \
--cc=behrensj@mit.edu \
--cc=cmuellner@linux.com \
--cc=devicetree@vger.kernel.org \
--cc=drew@beagleboard.org \
--cc=gfavor@ventanamicro.com \
--cc=hch@lst.de \
--cc=heiko@sntech.de \
--cc=huffman@cadence.com \
--cc=jscheid@ventanamicro.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=liush@allwinnertech.com \
--cc=maxime@cerno.tech \
--cc=mick@ics.forth.gr \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=philipp.tomsich@vrull.eu \
--cc=robh+dt@kernel.org \
--cc=rtrauben@gmail.com \
--cc=samuel@sholland.org \
--cc=wefu@redhat.com \
--cc=wens@csie.org \
--cc=xinhaoqu@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).