From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34D2DC433E0 for ; Sun, 31 May 2020 15:52:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B65C2074B for ; Sun, 31 May 2020 15:52:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1590940373; bh=oDHGnXcDGPNikMlB2Dv+Bax5Kyg7+1x/RgjKibTtM0c=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=yqiDFMnEpgK68t1I3JpApDaFh0R5xhfEgQy/VUDXoCvl+W+gEVg8eIy4Yh18T/4VX GcFy77PKYUc2alQ0JxnEy8QMsmGpyAoCtXry0dy5T2Ll/5oT+JnFNpOywiTxeVzjYJ sc5vPgCBcxcRVKV0GF6ICx1rBWte0lFQ7SffwCyE= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728147AbgEaPww (ORCPT ); Sun, 31 May 2020 11:52:52 -0400 Received: from mail.kernel.org ([198.145.29.99]:38066 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725912AbgEaPwv (ORCPT ); Sun, 31 May 2020 11:52:51 -0400 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 826B62074B for ; Sun, 31 May 2020 15:52:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1590940370; bh=oDHGnXcDGPNikMlB2Dv+Bax5Kyg7+1x/RgjKibTtM0c=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=kdwAyOZoN6tJxf8wzXTeWYtR5f0q+r8hv+E28zuXsiX6+c1GGNun9549+qqfr2P6v EHmy45ihYwWP4/fbWsW2l0uYbZgOCn85NgPB1bS6xDvUkmB56Lt8tW3UC3mbzCwJVk 0aVPNwi7N5AU6RIfgsJdrU1I8GFGsLHzPqM8IUdg= Received: by mail-lj1-f177.google.com with SMTP id z18so5035562lji.12 for ; Sun, 31 May 2020 08:52:50 -0700 (PDT) X-Gm-Message-State: AOAM532WNS9Mvm0v7NQ2SkS8/Hpflob85O0SyNxbdCtdE+rlxQC7h2V7 XaUhFMXUyXEUKiFpMaD9znd8QPeoUK5v/dJd+5w= X-Google-Smtp-Source: ABdhPJxc+UflSwuY3XbMSuBerzKlrHmG66opBdVixMEVxoI77AcKWDQYqR7zpJrgudE36zTC63+P7xoqyMWL0ypTKC0= X-Received: by 2002:a2e:9755:: with SMTP id f21mr8062431ljj.377.1590940368804; Sun, 31 May 2020 08:52:48 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Guo Ren Date: Sun, 31 May 2020 23:52:37 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH v4 00/13] riscv: Add vector ISA support To: Greentime Hu Cc: Guo Ren , Vincent Chen , Paul Walmsley , palmerdabbelt@google.com, linux-riscv , Linux Kernel Mailing List , oleg@redhat.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Greentime & Vincent, Thx for the dynamic vlen implementation. I've two suggestions: - Please give out glibc patches mail URL, we need to review them together. - We need to consider that not all processes need vectors. Most system processes do not have vector features, and we should not force save/restore vector for every process. On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote: > > This patchset is based on Guo Ren's v3 patchset to add dynamic vlen vector > support for all different kinds of vector length in riscv. To make this > happened we defined a new __riscv_v_state in sigcontext to save the vector > related registers. The datap pointer will be allocated dynamically in > kernel space and it will be put right after the __riscv_v_state data > structure to save all the vector registers in signal handler stack for user > space. So does the implementation in ptrace, they will be saved in ubuf > in which we put the __riscv_v_state data structure and datap pointer right > after it for vector registers. This patchset also fixes several bugs for > vector lazy save/restore and vtype not saving issue. It also adds new CSR > support for vector based on the 0.9 vector spec and clean up some unused > macros. > > This patchset is rebased to v5.7-rc4 and it is tested by running several > vector programs simultaneously. It also can get the correct ucontext_t in > signal handler and restore correct context after sigreturn. It is also > tested with ptrace() syscall to use PTRACE_GETREGSET/PTRACE_SETREGSET to > get/set the vector registers. I have tested vlen=128 and vlen=256 cases in > virt machine of qemu-system-riscv32 and qemu-system-riscv64 provided by > Zhiwei Lui. > > Since the vector spec is under developing, there might still need some > changes. For example the vle.v/vse.v instructions will be replaced with > proper instructions. The reason that I don't replace the instruction in > this patchset is because that the Qemu doesn't fully support 0.9 spec yet. > I have no simulator to test. We also like to discuss the default setting of > MINSIGSTKSZ and SIGSTKSZ. They might also need to set a proper number. They > are 2048 and 8096 now. Since the stack in signal will be reserved for > ucontext and the vector registers might be larger and larger someday, these > two macros will need to be defined as a proper value or maybe we should > provide a better mechanism to provide user to get a better default signal > stack size. > > > [1] https://github.com/romanheros/qemu/tree/linux-vector-dev > [2] https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html > [3] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc > > --- > Changelog V4 > - Support dynamic vlen > - Fix bugs: lazy save/resotre, not saving vtype > - Update VS bit offset based on latest vector spec > - Add new vector csr based on latest vector spec > - Code refine and removed unused macros > > Changelog V3 > - Rebase linux-5.6-rc3 and tested with qemu > - Seperate patches with Anup's advice > - Give out a ABI puzzle with unlimited vlen > > Changelog V2 > - Fixup typo "vecotr, fstate_save->vstate_save". > - Fixup wrong saved registers' length in vector.S. > - Seperate unrelated patches from this one. > > Greentime Hu (1): > ptrace: Use regset_size() for dynamic regset size. > > Guo Ren (11): > riscv: Separate patch for cflags and aflags > riscv: Rename __switch_to_aux -> fpu > riscv: Extending cpufeature.c to detect V-extension > riscv: Add new csr defines related to vector extension > riscv: Add vector feature to compile > riscv: Add has_vector/riscv_vsize to save vector features. > riscv: Reset vector register > riscv: Add vector struct and assembler definitions > riscv: Add task switch support for vector > riscv: Add ptrace vector support > riscv: Add sigcontext save/restore for vector > > Vincent Chen (1): > riscv: signal: Report signal frame size to userspace via auxv > > arch/riscv/Kconfig | 9 ++ > arch/riscv/Makefile | 19 ++-- > arch/riscv/include/asm/csr.h | 16 +++- > arch/riscv/include/asm/elf.h | 17 +++- > arch/riscv/include/asm/processor.h | 3 + > arch/riscv/include/asm/switch_to.h | 77 ++++++++++++++- > arch/riscv/include/uapi/asm/auxvec.h | 2 + > arch/riscv/include/uapi/asm/elf.h | 1 + > arch/riscv/include/uapi/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/ptrace.h | 13 +++ > arch/riscv/include/uapi/asm/sigcontext.h | 2 + > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/asm-offsets.c | 8 ++ > arch/riscv/kernel/cpufeature.c | 15 ++- > arch/riscv/kernel/entry.S | 2 +- > arch/riscv/kernel/head.S | 49 +++++++++- > arch/riscv/kernel/process.c | 40 ++++++++ > arch/riscv/kernel/ptrace.c | 114 +++++++++++++++++++++++ > arch/riscv/kernel/setup.c | 5 + > arch/riscv/kernel/signal.c | 108 ++++++++++++++++++++- > arch/riscv/kernel/vector.S | 84 +++++++++++++++++ > include/uapi/linux/elf.h | 1 + > kernel/ptrace.c | 11 ++- > 23 files changed, 573 insertions(+), 25 deletions(-) > create mode 100644 arch/riscv/kernel/vector.S > > -- > 2.26.2 > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/