From: Viresh Kumar <viresh.kumar@linaro.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Hein Tibosch <hein_tibosch@yahoo.es>,
Andrew Morton <akpm@linux-foundation.org>,
Hans-Christian Egtvedt <egtvedt@samfundet.no>,
Arnd Bergmann <arnd.bergmann@linaro.org>,
spear-devel <spear-devel@list.st.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"ludovic.desroches" <ludovic.desroches@atmel.com>,
Havard Skinnemoen <havard@skinnemoen.net>,
Nicolas Ferre <nicolas.ferre@atmel.com>
Subject: Re: [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register
Date: Mon, 3 Sep 2012 14:29:03 +0530 [thread overview]
Message-ID: <CAKohpomFDuTFVJ8SCmhRmPbCXMWdhD1Acjs5CAZD4aeqLZnurA@mail.gmail.com> (raw)
In-Reply-To: <CAHp75VcpzomoWb3+xOk=++BkUh5_cuXQTu8ZuDByjfX+pYmNCA@mail.gmail.com>
On 3 September 2012 14:19, Andy Shevchenko <andy.shevchenko@gmail.com> wrote:
> On Mon, Sep 3, 2012 at 11:30 AM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>> Which register are you talking about? This configuration is outside of DMAC
>> controller and i am not sure if dw DMAC controller can do 128 or 256
>> bit transfers.
> SRC_WIDTH & DST_WIDTH in CTLx. The field are 3 bit long. Acceptable
> values from 0 to 5.
> 2 corresponds to 32 bit transfers.
The field is 3 bit long but only allowable values are 0,1,2 & 3... This is what
i can check in my copy of dw_dmac manual.
4 and 5 aren't valid values.
next prev parent reply other threads:[~2012-09-03 8:59 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-02 17:54 [PATCH v4 2/3] dw_dmac: max_mem_width limits value for SRC/DST_TR_WID register Hein Tibosch
2012-09-03 8:25 ` Andy Shevchenko
2012-09-03 8:30 ` Viresh Kumar
2012-09-03 8:49 ` Andy Shevchenko
2012-09-03 8:59 ` Viresh Kumar [this message]
2012-09-03 13:06 ` Hein Tibosch
2012-09-04 6:38 ` Andy Shevchenko
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