From: Jagan Teki <jagan@amarulasolutions.com>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: daniel@ffwll.ch, linux-amlogic@lists.infradead.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
Date: Thu, 20 Jan 2022 16:33:22 +0530 [thread overview]
Message-ID: <CAMty3ZC9Cp=8=iF=KYCWjwb-wk+VrPBzH+6L14H6iZcSm3CZjA@mail.gmail.com> (raw)
In-Reply-To: <70d1af3f-bc00-4afd-1157-1cf70d3b2c88@baylibre.com>
On Wed, Jan 12, 2022 at 1:49 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> On 12/01/2022 08:24, Jagan Teki wrote:
> > Hi Neil,
> >
> > On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> >> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> >> Amlogic SoCs.
> >>
> >> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> >> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> >> Analog PHY in the proper way.
> >>
> >> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> >> is derived and feeds the ENCL encoder and the VIU pixel reader.
> >>
> >> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> >> DW-MIPI-DSI transceiver.
> >>
> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> >> ---
>
> [..]
>
> >> +
> >> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> >> + .bind = meson_dw_mipi_dsi_bind,
> >> + .unbind = meson_dw_mipi_dsi_unbind,
> >> +};
> >
> > Do you thought of non-component based meson DSI like STM DSI? It
> > require changes from meson drm but just to understand if you have any
> > such plan.
>
> I have no such plans for now, note this serie has been rewritten at [1] but still
> with based with components.
>
> If worth it, the plan is to get it with components and than yes if it's simpler
> drop components completely.
Dropping components make the pipeline well suited for bridges as we
are moving bridge-driven pipelines in other areas.
>
> I'll have a look at how ST does
ST has no components. As I said above, eventually there would be
common bridge driver for dw-mipi-dsi if meson and rockchip moving away
from components.
Thanks,
Jagan.
next prev parent reply other threads:[~2022-01-20 11:03 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
2020-09-07 8:18 ` [PATCH 1/6] dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs Neil Armstrong
2020-09-15 15:34 ` Rob Herring
2020-09-07 8:18 ` [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Neil Armstrong
2020-09-15 15:41 ` Rob Herring
2020-09-15 16:28 ` Neil Armstrong
2020-09-07 8:18 ` [PATCH 3/6] drm/meson: add support for VPU found in AXG SoCs Neil Armstrong
2020-09-07 8:18 ` [PATCH 4/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Neil Armstrong
2020-09-07 8:18 ` [PATCH 5/6] drm/meson: remove useless recursive components matching Neil Armstrong
2020-09-07 8:18 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
2020-09-07 8:43 ` Daniel Vetter
2020-09-07 8:44 ` Daniel Vetter
2020-09-07 9:03 ` Neil Armstrong
2020-09-07 18:03 ` Daniel Vetter
2020-09-08 8:06 ` Neil Armstrong
2020-09-08 8:46 ` Daniel Vetter
2020-09-17 7:14 ` Neil Armstrong
2020-09-17 11:32 ` Daniel Vetter
2022-01-12 7:24 ` Jagan Teki
2022-01-12 8:19 ` Neil Armstrong
2022-01-20 11:03 ` Jagan Teki [this message]
2022-01-20 13:28 ` Neil Armstrong
2022-01-07 14:55 [PATCH 0/6] drm/meson: add support for MIPI DSI Display Neil Armstrong
2022-01-07 14:55 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
2022-01-07 22:49 ` Martin Blumenstingl
2022-01-10 9:51 ` Neil Armstrong
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