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From: Emil Renner Berthing <kernel@esmil.dk>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Yury Norov <yury.norov@gmail.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	devicetree <devicetree@vger.kernel.org>,
	linux-clk <linux-clk@vger.kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Linus Walleij <linus.walleij@linaro.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Jiri Slaby <jirislaby@kernel.org>,
	Maximilian Luz <luzmaximilian@gmail.com>,
	Sagar Kadam <sagar.kadam@sifive.com>,
	Drew Fustini <drew@beagleboard.org>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Michael Zhu <michael.zhu@starfivetech.com>,
	Fu Wei <tekkamanninja@gmail.com>, Anup Patel <anup.patel@wdc.com>,
	Atish Patra <atish.patra@wdc.com>,
	Matteo Croce <mcroce@microsoft.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver
Date: Tue, 2 Nov 2021 20:58:57 +0100	[thread overview]
Message-ID: <CANBLGcyb=TAP0h2WuxBAjRvpN9n7Dt1Hvh5yE8NMOwm3ixZWuA@mail.gmail.com> (raw)
In-Reply-To: <CAHp75Ve-P8DR00mtRP_NkrXgB4nsZ+qBkgBen94iTcPqxQYUOg@mail.gmail.com>

On Tue, 2 Nov 2021 at 20:43, Andy Shevchenko <andy.shevchenko@gmail.com> wrote:
> +Cc: Yury (bitmap expert)
>
> On Tue, Nov 2, 2021 at 6:50 PM Emil Renner Berthing <kernel@esmil.dk> wrote:
> >
> > Add a driver for the StarFive JH7100 reset controller.
>
> ...
>
> > +#define BIT_MASK32(x) BIT((x) % 32)
>
> Possible namespace collision.
>
> ...
>
> > +/*
> > + * the registers work like a 32bit bitmap, so writing a 1 to the m'th bit of
> > + * the n'th ASSERT register asserts line 32n + m, and writing a 0 deasserts the
> > + * same line.
> > + * most reset lines have their status inverted so a 0 in the STATUS register
> > + * means the line is asserted and a 1 means it's deasserted. a few lines don't
> > + * though, so store the expected value of the status registers when all lines
> > + * are asserted.
> > + */
>
> Besides missing capitalization,

I'm confused. it was you who wanted all comments to capitalized the same..
64bi
if it sounds like bitmap, use bitmap.
> I have checked DT definitions and it seems you don't even need the
> BIT_MASK() macro,
>
> > +static const u32 jh7100_reset_asserted[4] = {
> > +       /* STATUS0 register */
> > +       BIT_MASK32(JH7100_RST_U74) |
> > +       BIT_MASK32(JH7100_RST_VP6_DRESET) |
> > +       BIT_MASK32(JH7100_RST_VP6_BRESET),
> > +       /* STATUS1 register */
> > +       BIT_MASK32(JH7100_RST_HIFI4_DRESET) |
> > +       BIT_MASK32(JH7100_RST_HIFI4_BRESET),
> > +       /* STATUS2 register */
> > +       BIT_MASK32(JH7100_RST_E24),
> > +       /* STATUS3 register */
> > +       0,
> > +};
>
> Yury, do we have any clever (clean) way to initialize a bitmap with
> particular bits so that it will be a constant from the beginning? If
> no, any suggestion what we can provide to such users?

The problem is, that even if we could initialize this without the
monstrosity in our last conversation a 64bit bitmap would still
produce worse code. As it is now it's simply a 32bit load and mask
with index and mask already calculated for the registers. In the
status callback the mask can even be folded into the register read
mask. With a 64bit bitmap you'd need to calculate new 64bit index and
masks, and then conditionally shift the bits into position.

If this reflection of the 32bit registers bothers you that much we
could alternatively do

static bool jh7100_reset_inverted(unsigned int idx)
{
  switch (idx) {
  case JH7100_RST_U74:
  case JH7100_RST_VP6_DRESET:
  ..
    return false;
  }
  return true;
}

It'd still produce worse code, but at least it would be readable.

/Emil

> ...
>
> > +       dev_dbg(rcdev->dev, "reset(%lu)\n", id);
>
> These debug messages are useless since one should use ftrace facility instead,
>
> --
> With Best Regards,
> Andy Shevchenko

  reply	other threads:[~2021-11-02 19:59 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-02 16:11 [PATCH v3 00/16] Basic StarFive JH7100 RISC-V SoC support Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 01/16] RISC-V: Add StarFive SoC Kconfig option Emil Renner Berthing
2021-11-08  9:24   ` Geert Uytterhoeven
2021-11-02 16:11 ` [PATCH v3 02/16] dt-bindings: timer: Add StarFive JH7100 clint Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 03/16] dt-bindings: interrupt-controller: Add StarFive JH7100 plic Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 04/16] dt-bindings: clock: starfive: Add JH7100 clock definitions Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 05/16] dt-bindings: clock: starfive: Add JH7100 bindings Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 06/16] clk: starfive: Add JH7100 clock generator driver Emil Renner Berthing
2021-11-02 19:43   ` Andy Shevchenko
2021-11-02 16:11 ` [PATCH v3 07/16] dt-bindings: reset: Add StarFive JH7100 reset definitions Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 08/16] dt-bindings: reset: Add Starfive JH7100 reset bindings Emil Renner Berthing
2021-11-08  9:25   ` Geert Uytterhoeven
2021-11-12 19:39   ` Rob Herring
2021-11-02 16:11 ` [PATCH v3 09/16] reset: starfive-jh7100: Add StarFive JH7100 reset driver Emil Renner Berthing
2021-11-02 19:42   ` Andy Shevchenko
2021-11-02 19:58     ` Emil Renner Berthing [this message]
2021-11-02 20:13       ` Andy Shevchenko
2021-11-02 21:17         ` Emil Renner Berthing
2021-11-04 12:15           ` Emil Renner Berthing
2021-11-08  9:17             ` Andy Shevchenko
2021-11-09  9:28               ` Emil Renner Berthing
2021-11-02 20:55       ` Yury Norov
2021-11-10 16:34         ` Yury Norov
2021-11-02 16:11 ` [PATCH v3 10/16] dt-bindings: pinctrl: Add StarFive pinctrl definitions Emil Renner Berthing
2021-11-12 19:40   ` Rob Herring
2021-11-02 16:11 ` [PATCH v3 11/16] dt-bindings: pinctrl: Add StarFive JH7100 bindings Emil Renner Berthing
2021-11-03  1:20   ` Rob Herring
2021-11-03 13:30     ` Emil Renner Berthing
2021-11-09  0:45   ` Linus Walleij
2021-11-11 23:04     ` Emil Renner Berthing
2021-11-21 23:19       ` Linus Walleij
2021-11-22 14:02         ` Emil Renner Berthing
2021-11-12 19:41   ` Rob Herring
2021-11-02 16:11 ` [PATCH v3 12/16] pinctrl: starfive: Add pinctrl driver for StarFive SoCs Emil Renner Berthing
2021-11-02 20:02   ` Andy Shevchenko
2021-11-02 20:07     ` Andy Shevchenko
2021-11-09  1:01       ` Linus Walleij
2021-11-09  9:21         ` Emil Renner Berthing
2021-11-09  9:33           ` Andy Shevchenko
2021-11-09  9:40             ` Emil Renner Berthing
2021-11-09 20:29               ` Linus Walleij
2021-11-09 21:04                 ` Emil Renner Berthing
2021-11-10  8:04                   ` Andy Shevchenko
2021-11-10 11:15                     ` Emil Renner Berthing
2021-11-02 20:35     ` Emil Renner Berthing
2021-11-03  9:12       ` Andy Shevchenko
2021-11-03 12:35         ` Emil Renner Berthing
2021-11-03 14:13           ` Andy Shevchenko
2021-11-09  0:54     ` Linus Walleij
2021-11-09  8:58       ` Andy Shevchenko
2021-11-02 16:11 ` [PATCH v3 13/16] dt-bindings: serial: snps-dw-apb-uart: Add JH7100 uarts Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 14/16] serial: 8250_dw: Add StarFive JH7100 quirk Emil Renner Berthing
2021-11-02 20:14   ` Andy Shevchenko
2021-11-08  9:32   ` Geert Uytterhoeven
2021-11-02 16:11 ` [PATCH v3 15/16] RISC-V: Add initial StarFive JH7100 device tree Emil Renner Berthing
2021-11-02 16:11 ` [PATCH v3 16/16] RISC-V: Add BeagleV Starlight Beta " Emil Renner Berthing

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